| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/04/07 01:32:53 lampret
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// Added get_gpr support for OR1200_RFRAM_GENERIC
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//
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// Revision 1.2 2002/08/12 05:38:11 lampret
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// Revision 1.2 2002/08/12 05:38:11 lampret
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// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
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// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
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//
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//
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// Revision 1.1 2002/03/28 19:59:55 lampret
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// Revision 1.1 2002/03/28 19:59:55 lampret
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// Added bench directory
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// Added bench directory
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| Line 221... |
Line 224... |
insns = insns + 1;
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insns = insns + 1;
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`endif
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`endif
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end
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end
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endtask
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endtask
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//
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// Write state of the OR1200 registers into a file; version for exception
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//
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task display_arch_state_except;
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reg [5:0] i;
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reg [31:0] r;
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integer j;
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begin
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`ifdef OR1200_DISPLAY_ARCH_STATE
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ref = ref + 1;
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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$fdisplay(fexe);
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get_gpr(i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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end
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$fdisplay(fexe);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
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$fwrite(fexe, "SR : %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
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$fwrite(fexe, "EPCR0: %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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insns = insns + 1;
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`endif
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end
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endtask
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integer iwb_progress;
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integer iwb_progress;
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reg [31:0] iwb_progress_addr;
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reg [31:0] iwb_progress_addr;
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//
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//
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// WISHBONE bus checker
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// WISHBONE bus checker
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//
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//
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| Line 323... |
Line 358... |
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
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if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
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#2;
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#2;
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if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
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if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
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&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
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&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
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display_arch_state;
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display_arch_state;
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else
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if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
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display_arch_state_except;
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
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get_gpr(3, r3);
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get_gpr(3, r3);
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$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
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$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
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$finish;
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$finish;
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end
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end
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
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$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
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`ifdef DBG_IF_MODEL
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xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
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`endif
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end
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
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get_gpr(3, r3);
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get_gpr(3, r3);
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$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
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$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
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end
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end
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
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