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Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/08/14 06:24:43 lampret
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// Fixed size of generic flash/sram to exactly 2MB
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//
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// Revision 1.2 2002/08/12 05:34:06 lampret
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// Revision 1.2 2002/08/12 05:34:06 lampret
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// Added SRAM_GENERIC
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// Added SRAM_GENERIC
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//
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//
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// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
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// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
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// First import of the "new" XESS XSV environment.
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// First import of the "new" XESS XSV environment.
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Line 140... |
// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [7:0] mem [2097151:0];
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reg [7:0] mem [2097151:0];
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wire [31:0] adr;
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wire [31:0] adr;
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`ifdef SRAM_GENERIC_REGISTERED
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`ifdef SRAM_GENERIC_REGISTERED
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reg wb_ack_o;
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reg wb_err_o;
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reg wb_err_o;
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reg [31:0] wb_dat_o;
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reg [31:0] prev_adr;
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reg [1:0] delay;
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`else
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wire [1:0] delay;
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`endif
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`endif
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wire wb_err;
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wire wb_err;
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//
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//
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// Aliases and simple assignments
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// Aliases and simple assignments
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//
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//
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assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)
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assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)
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assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
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assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
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`ifdef SRAM_GENERIC_REGISTERED
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//
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//
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// Reading from SRAM model
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// Reading from SRAM model
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//
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//
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always @(posedge wb_rst_i or posedge wb_clk_i)
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if (wb_rst_i)
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wb_dat_o <= #1 32'h0000_0000;
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else begin
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wb_dat_o[7:0] <= #1 mem[adr+3];
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wb_dat_o[15:8] <= #1 mem[adr+2];
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wb_dat_o[23:16] <= #1 mem[adr+1];
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wb_dat_o[31:24] <= #1 mem[adr+0];
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end
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`else
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assign wb_dat_o[7:0] = mem[adr+3];
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assign wb_dat_o[7:0] = mem[adr+3];
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assign wb_dat_o[15:8] = mem[adr+2];
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assign wb_dat_o[15:8] = mem[adr+2];
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assign wb_dat_o[23:16] = mem[adr+1];
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assign wb_dat_o[23:16] = mem[adr+1];
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assign wb_dat_o[31:24] = mem[adr+0];
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assign wb_dat_o[31:24] = mem[adr+0];
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`endif
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//
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//
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// Writing to SRAM model
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// Writing to SRAM model
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//
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//
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always @(posedge wb_rst_i or posedge wb_clk_i)
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always @(posedge wb_rst_i or posedge wb_clk_i)
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Line 182... |
`ifdef SRAM_GENERIC_REGISTERED
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`ifdef SRAM_GENERIC_REGISTERED
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//
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//
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// WB Acknowledge
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// WB Acknowledge
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//
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//
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i) begin
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wb_ack_o <= #1 1'b0;
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delay <= #1 2'd3;
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else
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prev_adr <= #1 32'h0000_0000;
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
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end
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else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
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delay <= #1 delay - 2'd1;
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else if (wb_ack_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
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delay <= #1 2'd3; // delay ... can range from 3 to 0
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prev_adr <= #1 wb_adr_i;
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end
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`else
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`else
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assign wb_ack_o = wb_cyc_i & wb_stb_i;
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assign delay = 2'd0;
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`endif
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assign wb_ack_o = wb_cyc_i & wb_stb_i & (delay == 2'd0)
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`ifdef SRAM_GENERIC_REGISTERED
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& (wb_adr_i == prev_adr)
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`endif
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`endif
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;
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`ifdef SRAM_GENERIC_REGISTERED
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`ifdef SRAM_GENERIC_REGISTERED
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//
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//
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// WB Error
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// WB Error
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//
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//
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| Line 211... |
Line 216... |
`else
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`else
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assign wb_err_o = wb_err;
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assign wb_err_o = wb_err;
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`endif
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`endif
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//
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//
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// Flash i/f monitor
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// SRAM i/f monitor
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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integer fsram;
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integer fsram;
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initial fsram = $fopen("sram.log");
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initial fsram = $fopen("sram.log");
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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