| Line 88... |
Line 88... |
//
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//
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`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
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`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
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//
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//
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// Traffic Cop Top
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// Traffic Cop Top
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// There are two channels to tc_top. One channel
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// is dedicated to connecting the initiators to target 0
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// only. The second channel is is for connecting the initiators
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// to targets 2-8. Additional comments are added below
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//
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//
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module tc_top (
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module tc_top (
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wb_clk_i,
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wb_clk_i,
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wb_rst_i,
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wb_rst_i,
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| Line 554... |
Line 550... |
// Internal wires & registers
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// Internal wires & registers
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//
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//
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|
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//
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//
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// Outputs for initiators from both mi_to_st blocks
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// Outputs for initiators from both mi_to_st blocks
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//Wires prefixed with x refer to a channel that only contains
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//target 0.
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//Wires prefixed with y refers to a second channel that contains
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//targets 1-8
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//
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//
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wire [`TC_DW-1:0] xi0_wb_dat_o;
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wire [`TC_DW-1:0] xi0_wb_dat_o;
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wire xi0_wb_ack_o;
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wire xi0_wb_ack_o;
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wire xi0_wb_err_o;
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wire xi0_wb_err_o;
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wire [`TC_DW-1:0] xi1_wb_dat_o;
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wire [`TC_DW-1:0] xi1_wb_dat_o;
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| Line 625... |
Line 617... |
wire z_wb_ack_t;
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wire z_wb_ack_t;
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wire z_wb_err_t;
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wire z_wb_err_t;
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//
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//
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// Outputs for initiators are ORed from both mi_to_st blocks
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// Outputs for initiators are ORed from both mi_to_st blocks
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//The two separate channels going back to the initiator are
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//merged here
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//Remember x is target 0 only. y is targets 2-8
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//
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//
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//
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assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
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assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
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assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
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assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
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assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
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assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
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assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
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assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
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| Line 657... |
Line 645... |
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
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assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
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assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
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assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
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//
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//
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// From initiators to target 0
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// From initiators to target 0
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//This defines a channel going only to target 0.
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//This forms a multiplexing arbiter. The module gets used in two places.
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//This instance is used to define a dedicated channel to target 0.
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//
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//
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tc_mi_to_st #(t0_addr_w, t0_addr,
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tc_mi_to_st #(t0_addr_w, t0_addr,
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0, t0_addr_w, t0_addr) t0_ch(
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0, t0_addr_w, t0_addr) t0_ch(
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.wb_rst_i(wb_rst_i),
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| Line 769... |
Line 754... |
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);
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);
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//
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//
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//From initiators to targets 1-8 (upper part)
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//From initiators to targets 1-8 (upper part)
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//This instance is used to define a second channel for accessing
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//targets 1-8. Note the "z-wires" that connect
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//this instance to the t18_ch_lower instance defined
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//further down
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//
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//
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tc_mi_to_st #(t1_addr_w, t1_addr,
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tc_mi_to_st #(t1_addr_w, t1_addr,
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1, t28c_addr_w, t28_addr) t18_ch_upper(
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1, t28c_addr_w, t28_addr) t18_ch_upper(
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.wb_rst_i(wb_rst_i),
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| Line 882... |
Line 863... |
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);
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);
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//
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//
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// From initiators to targets 1-8 (lower part)
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// From initiators to targets 1-8 (lower part)
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//This instance is used to route the signals
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//from tc18_ch_upper to the destination target.
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//
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//
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tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
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tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
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t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
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t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
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.i0_wb_cyc_i(z_wb_cyc_i),
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.i0_wb_cyc_i(z_wb_cyc_i),
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