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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [tc_top.v] - Diff between revs 746 and 796

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Rev 746	Rev 796
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
	`// First import of the "new" XESS XSV environment.`
	`//`
	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
Line 859...	Line 863...
`//`	`//`
`// From initiators to targets 1-8 (lower part)`	`// From initiators to targets 1-8 (lower part)`
`//`	`//`
`tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,`	`tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,`
`t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(`	`t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(`
`.wb_clk_i(wb_clk_i),`
`.wb_rst_i(wb_rst_i),`

`.i0_wb_cyc_i(z_wb_cyc_i),`	`.i0_wb_cyc_i(z_wb_cyc_i),`
`.i0_wb_stb_i(z_wb_stb_i),`	`.i0_wb_stb_i(z_wb_stb_i),`
`.i0_wb_cab_i(z_wb_cab_i),`	`.i0_wb_cab_i(z_wb_cab_i),`
`.i0_wb_adr_i(z_wb_adr_i),`	`.i0_wb_adr_i(z_wb_adr_i),`
Line 1403...	Line 1405...

`//`	`//`
`// Single initiator to multiple targets`	`// Single initiator to multiple targets`
`//`	`//`
`module tc_si_to_mt (`	`module tc_si_to_mt (`
`wb_clk_i,`
`wb_rst_i,`

`i0_wb_cyc_i,`	`i0_wb_cyc_i,`
`i0_wb_stb_i,`	`i0_wb_stb_i,`
`i0_wb_cab_i,`	`i0_wb_cab_i,`
`i0_wb_adr_i,`	`i0_wb_adr_i,`
Line 1524...	Line 1524...
`parameter t7_addr = 3'd7;`	`parameter t7_addr = 3'd7;`

`//`	`//`
`// I/O Ports`	`// I/O Ports`
`//`	`//`
`input wb_clk_i;`
`input wb_rst_i;`

`//`	`//`
`// WB slave i/f connecting initiator 0`	`// WB slave i/f connecting initiator 0`
`//`	`//`
`input i0_wb_cyc_i;`	`input i0_wb_cyc_i;`

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [tc_top.v] - Diff between revs 746 and 796