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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [xsv_fpga_top.v] - Diff between revs 947 and 1133

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Rev 947	Rev 1133
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/08/12 05:35:12 lampret`
	`// rty_i are unused - tied to zero.`
	`//`
`// Revision 1.5 2002/03/29 20:58:51 lampret`	`// Revision 1.5 2002/03/29 20:58:51 lampret`
`// Changed hardcoded address for fake MC to use a define.`	`// Changed hardcoded address for fake MC to use a define.`
`//`	`//`
`// Revision 1.4 2002/03/29 16:30:47 lampret`	`// Revision 1.4 2002/03/29 16:30:47 lampret`
`// Fixed port names that changed.`	`// Fixed port names that changed.`
Line 57...	Line 60...
`// Fixed some typos`	`// Fixed some typos`
`//`	`//`
`//`	`//`

`include "xsv_fpga_defines.v"	`include "xsv_fpga_defines.v"
	`include "bench_defines.v"

`module xsv_fpga_top (`	`module xsv_fpga_top (`

`//`	`//`
`// Global signals`	`// Global signals`
Line 507...	Line 511...
`reg wb_rst;`	`reg wb_rst;`

`//`	`//`
`// Global clock`	`// Global clock`
`//`	`//`
	`ifdef OR1200_CLMODE_1TO2
	`reg wb_clk;`
	`else
`wire wb_clk;`	`wire wb_clk;`
	`endif

`//`	`//`
`// Reset debounce`	`// Reset debounce`
`//`	`//`
`always @(posedge wb_clk or negedge rstn)`	`always @(posedge wb_clk or negedge rstn)`
Line 525...	Line 533...
`//`	`//`
`always @(posedge wb_clk)`	`always @(posedge wb_clk)`
`wb_rst <= #1 rst_r;`	`wb_rst <= #1 rst_r;`

`//`	`//`
	`// This is purely for testing 1/2 WB clock`
	`// This should never be used when implementing in`
	`// an FPGA.`
	`//`
	`ifdef OR1200_CLMODE_1TO2
	`initial wb_clk = 0;`
	`//always @(posedge clk)`
	`// wb_clk = ~wb_clk;`
	`always @(clk)`
	`wb_clk = clk;`

	`else
	`//`
`// Some Xilinx P&R tools need this`	`// Some Xilinx P&R tools need this`
`//`	`//`
`ifdef TARGET_VIRTEX	`ifdef TARGET_VIRTEX
`IBUFG IBUFG1 (`	`IBUFG IBUFG1 (`
`.O ( wb_clk ),`	`.O ( wb_clk ),`
`.I ( clk )`	`.I ( clk )`
`);`	`);`
`else	`else
`assign wb_clk = clk;`	`assign wb_clk = clk;`
`endif	`endif
	`endif // OR1200_CLMODE_1TO2

`//`	`//`
`// SRAM tri-state data`	`// SRAM tri-state data`
`//`	`//`
`assign sram_r_d = sram_d_oe ? sram_r_d_o : 16'hzzzz;`	`assign sram_r_d = sram_d_oe ? sram_r_d_o : 16'hzzzz;`
Line 1303...	Line 1325...
`.t8_wb_dat_i ( 32'h0000_0000 ),`	`.t8_wb_dat_i ( 32'h0000_0000 ),`
`.t8_wb_ack_i ( 1'b0 ),`	`.t8_wb_ack_i ( 1'b0 ),`
`.t8_wb_err_i ( 1'b1 )`	`.t8_wb_err_i ( 1'b1 )`
`);`	`);`

	`//initial begin`
	`// $dumpvars(0);`
	`// $dumpfile("dump.vcd");`
	`//end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [xsv_fpga_top.v] - Diff between revs 947 and 1133