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Line 66... |
// Fixed some typos
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// Fixed some typos
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//
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//
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//
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//
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`include "xsv_fpga_defines.v"
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`include "xsv_fpga_defines.v"
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// synopsys translate_off
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`include "bench_defines.v"
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`include "bench_defines.v"
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// synopsys translate_on
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module xsv_fpga_top (
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module xsv_fpga_top (
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//
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//
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// Global signals
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// Global signals
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| Line 607... |
Line 604... |
// This way we have flash at base address 0x0
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// This way we have flash at base address 0x0
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// during reset vector execution (boot). First
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// during reset vector execution (boot). First
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// access to real Flash area will automatically
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// access to real Flash area will automatically
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// move SRAM to 0x0.
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// move SRAM to 0x0.
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//
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//
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`ifdef NO_FLASH_INSTRUCION_ADDR
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always prefix_flash <= #1 1'b0;
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`else
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always @(posedge wb_clk or negedge rstn)
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always @(posedge wb_clk or negedge rstn)
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if (!rstn)
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if (!rstn)
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prefix_flash <= #1 1'b1;
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prefix_flash <= #1 1'b1;
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else if (wb_rim_cyc_o &&
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else if (wb_rim_cyc_o &&
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(wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
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(wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
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prefix_flash <= #1 1'b0;
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prefix_flash <= #1 1'b0;
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`endif
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assign wb_rif_adr = prefix_flash ? {`APP_ADDR_FLASH, wb_rim_adr_o[31-`APP_ADDR_DEC_W:0]}
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assign wb_rif_adr = prefix_flash ? {`APP_ADDR_FLASH, wb_rim_adr_o[31-`APP_ADDR_DEC_W:0]}
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: wb_rim_adr_o;
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: wb_rim_adr_o;
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assign wb_rdm_ack_i = (wb_rdm_adr_o[31:28] == `APP_ADDR_FAKEMC) &&
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assign wb_rdm_ack_i = (wb_rdm_adr_o[31:28] == `APP_ADDR_FAKEMC) &&
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wb_rdm_cyc_o && wb_rdm_stb_o ? 1'b1 : wb_rdm_ack;
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wb_rdm_cyc_o && wb_rdm_stb_o ? 1'b1 : wb_rdm_ack;
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| Line 874... |
Line 866... |
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// Debug
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// Debug
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.dbg_stall_i ( dbg_stall ),
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.dbg_stall_i ( dbg_stall ),
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_adr_i ( dbg_adr ),
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.dbg_adr_i ( dbg_adr ),
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.dbg_op_i ( dbg_op ),
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.dbg_ewt_i ( 1'b0 ),
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.dbg_ewt_i ( 1'b0 ),
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.dbg_lss_o ( dbg_lss ),
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.dbg_lss_o ( dbg_lss ),
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.dbg_is_o ( dbg_is ),
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.dbg_is_o ( dbg_is ),
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.dbg_wp_o ( dbg_wp ),
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.dbg_wp_o ( dbg_wp ),
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.dbg_bp_o ( dbg_bp ),
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.dbg_bp_o ( dbg_bp ),
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.dbg_dat_o ( dbg_dat_risc ),
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.dbg_dat_o ( dbg_dat_risc ),
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.dbg_ack_o ( ),
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.dbg_stb_i ( dbg_op[2] ),
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.dbg_we_i ( dbg_op[0] ),
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// Power Management
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// Power Management
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.pm_clksd_o ( ),
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.pm_clksd_o ( ),
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.pm_cpustall_i ( 1'b0 ),
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.pm_cpustall_i ( 1'b0 ),
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.pm_dc_gate_o ( ),
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.pm_dc_gate_o ( ),
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