URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [xsv_fpga_top.v] - Diff between revs 792 and 797

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 792	Rev 797
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/03/29 16:30:47 lampret`
	`// Fixed port names that changed.`
	`//`
`// Revision 1.3 2002/03/29 15:50:03 lampret`	`// Revision 1.3 2002/03/29 15:50:03 lampret`
`// Added response from memory controller (addr 0x60000000)`	`// Added response from memory controller (addr 0x60000000)`
`//`	`//`
`// Revision 1.2 2002/03/21 17:39:16 lampret`	`// Revision 1.2 2002/03/21 17:39:16 lampret`
`// Fixed some typos`	`// Fixed some typos`
Line 581...	Line 584...
`else if (wb_rim_cyc_o &&`	`else if (wb_rim_cyc_o &&`
(wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))	(wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
`prefix_flash <= #1 1'b0;`	`prefix_flash <= #1 1'b0;`
assign wb_rif_adr = prefix_flash ? {`APP_ADDR_FLASH, wb_rim_adr_o[31-`APP_ADDR_DEC_W:0]}	assign wb_rif_adr = prefix_flash ? {`APP_ADDR_FLASH, wb_rim_adr_o[31-`APP_ADDR_DEC_W:0]}
`: wb_rim_adr_o;`	`: wb_rim_adr_o;`
`assign wb_rdm_ack_i = (wb_rdm_adr_o[31:28] == 4'h6) &&`	assign wb_rdm_ack_i = (wb_rdm_adr_o[31:28] == `APP_ADDR_FAKEMC) &&
`wb_rdm_cyc_o && wb_rdm_stb_o ? 1'b1 : wb_rdm_ack;`	`wb_rdm_cyc_o && wb_rdm_stb_o ? 1'b1 : wb_rdm_ack;`

`//`	`//`
`// Instantiation of the VGA CRT controller`	`// Instantiation of the VGA CRT controller`
`//`	`//`

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [xsv_fpga_top.v] - Diff between revs 792 and 797