| Line 8... |
Line 8... |
Bottom half will be used for this program, the rest
|
Bottom half will be used for this program, the rest
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will be used for testing */
|
will be used for testing */
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#define FLASH_START 0x04000000
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#define FLASH_START 0x04000000
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#define FLASH_SIZE 0x00200000
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#define FLASH_SIZE 0x00200000
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#define RAM_START 0x00000000
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#define RAM_START 0x00000000
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#define RAM_SIZE 0x00200000
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#define RAM_SIZE 0x00400000
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|
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/* MMU page size */
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/* MMU page size */
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#define PAGE_SIZE 8192
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#define PAGE_SIZE 8192
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|
|
/* Number of DTLB sets used (power of 2, max is 256) */
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/* Number of DTLB sets used (power of 2, max is 256) */
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| Line 35... |
Line 35... |
#define TLB_TEXT_SET_NB 6
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#define TLB_TEXT_SET_NB 6
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#define TLB_DATA_SET_NB 6
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#define TLB_DATA_SET_NB 6
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|
|
#define TLB_CODE_MASK 0xffffc000
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#define TLB_CODE_MASK 0xffffc000
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#define TLB_PR_MASK 0x00003fff
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#define TLB_PR_MASK 0x00003fff
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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SPR_DTLBTR_URE | \
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#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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|
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#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_CI | \
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#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
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SPR_ITLBTR_SXE | \
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SPR_ITLBTR_UXE )
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SPR_ITLBTR_UXE )
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|
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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|
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| Line 88... |
Line 87... |
extern int store_acc_16 (unsigned long add);
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extern int store_acc_16 (unsigned long add);
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extern int load_b_acc_32 (unsigned long add);
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extern int load_b_acc_32 (unsigned long add);
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extern int int_trigger (void);
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extern int int_trigger (void);
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extern int int_loop (void);
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extern int int_loop (void);
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extern int jump_back (void);
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extern int jump_back (void);
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extern int ic_invalidate (void);
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|
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/* Local functions prototypes */
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/* Local functions prototypes */
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void dmmu_disable (void);
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void dmmu_disable (void);
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void immu_disable (void);
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void immu_disable (void);
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|
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| Line 407... |
Line 407... |
mtspr (SPR_ITLBMR_BASE(0) + i, ea & SPR_ITLBMR_VPN | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea & SPR_ITLBMR_VPN | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta & SPR_ITLBTR_PPN| ITLB_PR_NOLIMIT);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta & SPR_ITLBTR_PPN| ITLB_PR_NOLIMIT);
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}
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}
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI;
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itlb_val = 0;
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 430... |
Line 430... |
ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_pc == ea);
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ASSERT(except_pc == ea);
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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itlb_val = SPR_ITLBTR_SXE;
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 446... |
Line 446... |
ASSERT(except_mask == (1 << V_IPF));
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ASSERT(except_mask == (1 << V_IPF));
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ASSERT(except_pc == ea);
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ASSERT(except_pc == ea);
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI;
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itlb_val = 0;
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 462... |
Line 462... |
ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_pc == ea + 4);
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ASSERT(except_pc == ea + 4);
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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itlb_val = SPR_ITLBTR_SXE;
|
|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 516... |
Line 516... |
mtspr (SPR_DTLBMR_BASE(0) + i, ea & SPR_DTLBMR_VPN | SPR_ITLBMR_V);
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mtspr (SPR_DTLBMR_BASE(0) + i, ea & SPR_DTLBMR_VPN | SPR_ITLBMR_V);
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mtspr (SPR_DTLBTR_BASE(0) + i, ta & SPR_DTLBTR_PPN | DTLB_PR_NOLIMIT);
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mtspr (SPR_DTLBTR_BASE(0) + i, ta & SPR_DTLBTR_PPN | DTLB_PR_NOLIMIT);
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}
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}
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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dtlb_val = SPR_DTLBTR_CI;
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dtlb_val = 0;
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 540... |
Line 540... |
ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
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ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
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ASSERT(except_ea == ea);
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ASSERT(except_ea == ea);
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ASSERT(ret == 0x12345678);
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ASSERT(ret == 0x12345678);
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|
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
|
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
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dtlb_val = SPR_DTLBTR_SRE;
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|
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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| Line 618... |
Line 618... |
except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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|
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/* Set IMMU translation */
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/* Set IMMU translation */
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ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
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ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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itlb_val = SPR_ITLBTR_SXE;
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mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val);
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mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val);
|
|
|
/* Enable IMMU */
|
/* Enable IMMU */
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immu_enable ();
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immu_enable ();
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| Line 645... |
Line 645... |
|
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/* Copy jump instruction to last location of RAM */
|
/* Copy jump instruction to last location of RAM */
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ea = RAM_START + RAM_SIZE - 8;
|
ea = RAM_START + RAM_SIZE - 8;
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memcpy((void *)ea, (void *)&jump_back, 8);
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memcpy((void *)ea, (void *)&jump_back, 8);
|
|
|
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// ic_invalidate ();
|
|
|
/* Check if there was bus error exception */
|
/* Check if there was bus error exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
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ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_pc == ea + 4);
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ASSERT(except_pc == ea + 4);
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| Line 660... |
Line 662... |
except_pc = 0;
|
except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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|
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/* Set DMMU translation */
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/* Set DMMU translation */
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ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
|
ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
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dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
|
dtlb_val = SPR_DTLBTR_SRE;
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mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val);
|
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val);
|
|
|
/* Enable DMMU */
|
/* Enable DMMU */
|
dmmu_enable ();
|
dmmu_enable ();
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| Line 882... |
Line 884... |
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI;
|
itlb_val = 0;
|
|
|
/* Invalidate all entries in DTLB */
|
/* Invalidate all entries in DTLB */
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
| Line 904... |
Line 906... |
|
|
/* Init tick timer */
|
/* Init tick timer */
|
tick_init (1, 1);
|
tick_init (1, 1);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
dtlb_val = SPR_DTLBTR_CI;
|
dtlb_val = 0;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
| Line 1125... |
Line 1127... |
|
|
/* ITLB exception test */
|
/* ITLB exception test */
|
itlb_test (); // OK
|
itlb_test (); // OK
|
|
|
/* DTLB exception test */
|
/* DTLB exception test */
|
// dtlb_test (); // OK [with enabled IC/DC it fails on or1ksim]
|
dtlb_test (); // OK [with enabled IC/DC it fails on or1ksim]
|
|
|
/* Bus error exception test */
|
/* Bus error exception test */
|
// buserr_test (); // Doesn't work on or1ksim
|
buserr_test (); // Doesn't work on or1ksim
|
|
|
/* Illegal insn test */
|
/* Illegal insn test */
|
illegal_insn_test (); // OK
|
illegal_insn_test (); // OK
|
|
|
/* Alignment test */
|
/* Alignment test */
|
| Line 1143... |
Line 1145... |
|
|
/* Range test */
|
/* Range test */
|
// range_test (); // Doesn't work on or1ksim
|
// range_test (); // Doesn't work on or1ksim
|
|
|
/* Exception priority test */
|
/* Exception priority test */
|
// except_priority_test (); // Doesn't work on or1ksim
|
except_priority_test (); // Doesn't work on or1ksim
|
|
|
report (0xdeaddead);
|
report (0xdeaddead);
|
exit (0);
|
exit (0);
|
|
|
return 0;
|
return 0;
|
