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[/] [or1k_old/] [trunk/] [rc203soc/] [rtl/] [verilog/] [soc.v] - Diff between revs 1327 and 1494

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Rev 1327 Rev 1494
Line 41... Line 41... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.1.1.1  2004/12/13 17:14:31  jcastillo
 
 
 
// Firt import of OR1200 over Celoxica RC203 platform
 
 
 
//
 
 
 
 
 
// synopsys translate_off
 
// synopsys translate_off
 
`include "timescale.v"
 
`include "timescale.v"
 
// synopsys translate_on
 
// synopsys translate_on
 
 
 
 
Line 79... Line 82... 
   //UART ports
 
   //UART ports
 
   uart_stx,uart_srx,
 
   uart_stx,uart_srx,
 
 
 
 
 
   //JTAG ports
 
   //JTAG ports
 
   jtag_tdi,jtag_tms,jtag_tck,
 
   jtag_tdi,jtag_tms,jtag_tck,
 
   jtag_tdo
 
   jtag_tdo,
 
 
 
 
 
 
 
   //Ethernet ports
 
 
 
   eth_nREAD,eth_nWRITE,
 
 
 
   eth_address,eth_data,
 
 
 
   eth_nBE,eth_reset
 
 
 
 
 
   );
 
   );
 
 
 
 
 
   parameter dw = `OR1200_OPERAND_WIDTH;
 
   parameter dw = `OR1200_OPERAND_WIDTH;
 
   parameter aw = `OR1200_OPERAND_WIDTH;
 
   parameter aw = `OR1200_OPERAND_WIDTH;
Line 105... Line 113... 
   input         jtag_tdi;
 
   input         jtag_tdi;
 
   input         jtag_tms;
 
   input         jtag_tms;
 
   input         jtag_tck;
 
   input         jtag_tck;
 
   output        jtag_tdo;
 
   output        jtag_tdo;
 
 
 
 
 
 
 
   //
 
 
 
   // SMC91111 PINS
 
 
 
   //
 
 
 
   output        eth_nREAD;
 
 
 
   output        eth_nWRITE;
 
 
 
   output [2:0]  eth_address;
 
 
 
   inout  [15:0] eth_data;   //INOUT
 
 
 
   output [1:0]  eth_nBE;
 
 
 
   output        eth_reset;
 
 
 
 
 
assign sram_clk=clk;
 
assign sram_clk=clk;
 
 
 
 
 
//Declaring signals
 
//Declaring signals
 
wire    [1:0]             clmode;        // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
wire    [1:0]             clmode;        // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
Line 198... Line 215... 
// Wires to internal ROM
 
// Wires to internal ROM
 
//
 
//
 
wire [14:0]   rom_address;
 
wire [14:0]   rom_address;
 
wire [31:0]   rom_data;
 
wire [31:0]   rom_data;
 
 
 
 
 
 
 
//
 
 
 
//  Ethernet Controller
 
 
 
//
 
 
 
wire  [31:0]  eth_wb_dat_i;
 
 
 
wire  [31:0]  eth_wb_dat_o;
 
 
 
wire  [31:0]  eth_wb_adr;
 
 
 
wire  [3:0]   eth_wb_sel;
 
 
 
wire          eth_wb_we;
 
 
 
wire          eth_wb_cyc;
 
 
 
wire          eth_wb_stb;
 
 
 
wire          eth_wb_ack;
 
 
 
 
 
//
 
//
 
// Debug core master i/f wires
 
// Debug core master i/f wires
 
//
 
//
 
wire  [31:0]  wb_dm_adr_o;
 
wire  [31:0]  wb_dm_adr_o;
Line 242... Line 269... 
// during reset vector execution (boot). First
 
// during reset vector execution (boot). First
 
// access to real Flash area will automatically
 
// access to real Flash area will automatically
 
// move SRAM to 0x0.
 
// move SRAM to 0x0.
 
//
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
reg          prefix_flash;
 
reg          prefix_flash;
 
wire  [31:0] iwb_fake_adr;
 
wire  [31:0] iwb_fake_adr;
 
wire         dwb_ack_s;
 
wire         dwb_ack_s;
 
//
 
 
 
// Use this to boot from ROM
 
 
 
//
 
 
 
//always @(posedge clk or posedge reset)
 
//always @(posedge clk or posedge reset)
 
//      if (reset)
 
//      if (reset)
 
//      begin
 
//      begin
 
//              prefix_flash <= #1 1'b1;
 
//              prefix_flash <= #1 1'b1;
 
//      end     
//      end
Line 262... Line 285... 
//              prefix_flash <= #1 1'b0;
 
//              prefix_flash <= #1 1'b0;
 
//      end     
//      end     
//assign iwb_fake_adr = prefix_flash ? {`APP_ADDR_FLASH, iwb_adr[31-`APP_ADDR_DEC_W:0]} : iwb_adr;
 
//assign iwb_fake_adr = prefix_flash ? {`APP_ADDR_FLASH, iwb_adr[31-`APP_ADDR_DEC_W:0]} : iwb_adr;
 
//assign dwb_ack = (dwb_adr[31:28] == `APP_ADDR_FAKEMC) && dwb_cyc && dwb_stb ? 1'b1 : dwb_ack_s;             
//assign dwb_ack = (dwb_adr[31:28] == `APP_ADDR_FAKEMC) && dwb_cyc && dwb_stb ? 1'b1 : dwb_ack_s;             
 
 
 
 
//
 
 
 
// Use this to boot from RAM
 
 
 
//
 
 
 
assign iwb_fake_adr = iwb_adr;
 
assign iwb_fake_adr = iwb_adr;
 
assign dwb_ack =  dwb_ack_s;
 
assign dwb_ack =  dwb_ack_s;
 
 
 
 
 
//
 
//
 
// Instantiation of the Traffic COP
 
// Instantiation of the Traffic COP
Line 425... Line 445... 
        .t2_wb_dat_i ( 32'h0000_0000 ),
 
        .t2_wb_dat_i ( 32'h0000_0000 ),
 
        .t2_wb_ack_i ( 1'b0 ),
 
        .t2_wb_ack_i ( 1'b0 ),
 
        .t2_wb_err_i ( 1'b1 ),
 
        .t2_wb_err_i ( 1'b1 ),
 
 
 
 
 
        // WISHBONE Target 3
 
        // WISHBONE Target 3
 
        .t3_wb_cyc_o ( ),
 
        .t3_wb_cyc_o ( eth_wb_cyc ),
 
        .t3_wb_stb_o ( ),
 
        .t3_wb_stb_o ( eth_wb_stb ),
 
        .t3_wb_cab_o ( ),
 
        .t3_wb_cab_o ( eth_wb_cab ),
 
        .t3_wb_adr_o ( ),
 
        .t3_wb_adr_o ( eth_wb_adr ),
 
        .t3_wb_sel_o ( ),
 
        .t3_wb_sel_o ( eth_wb_sel ),
 
        .t3_wb_we_o  ( ),
 
        .t3_wb_we_o  ( eth_wb_we  ),
 
        .t3_wb_dat_o ( ),
 
        .t3_wb_dat_o ( eth_wb_dat_i ),
 
        .t3_wb_dat_i ( 32'h0000_0000 ),
 
        .t3_wb_dat_i ( eth_wb_dat_o ),
 
        .t3_wb_ack_i ( 1'b0 ),
 
        .t3_wb_ack_i ( eth_wb_ack ),
 
        .t3_wb_err_i ( 1'b1 ),
 
        .t3_wb_err_i ( 1'b0 ),
 
 
 
 
 
        // WISHBONE Target 4
 
        // WISHBONE Target 4
 
        .t4_wb_cyc_o ( ),
 
        .t4_wb_cyc_o ( ),
 
        .t4_wb_stb_o ( ),
 
        .t4_wb_stb_o ( ),
 
        .t4_wb_cab_o ( ),
 
        .t4_wb_cab_o ( ),
Line 708... Line 728... 
        .address  ( rom_address ),
 
        .address  ( rom_address ),
 
        .data     ( rom_data )
 
        .data     ( rom_data )
 
);
 
);
 
 
 
 
 
//
 
//
 
 
 
// Instantiation of the Ethernet SMC91111 Interface
 
 
 
//                           
 
 
wb_eth_controller  wb_eth_controller(
 
 
 
        .clk(clk),
 
 
 
        .reset(reset),
 
 
 
 
 
 
 
        .wb_stb_i ( eth_wb_stb ),
 
 
 
        .wb_dat_o ( eth_wb_dat_o ),
 
 
 
        .wb_dat_i ( eth_wb_dat_i ),
 
 
 
        .wb_ack_o ( eth_wb_ack ),
 
 
 
        .wb_adr_i ( eth_wb_adr ),
 
 
 
        .wb_we_i  ( eth_wb_we ),
 
 
 
        .wb_cyc_i ( eth_wb_cyc ),
 
 
 
        .wb_sel_i ( eth_wb_sel ),
 
 
 
 
 
 
 
        .eth_nREAD(eth_nREAD),
 
 
 
                .eth_nWRITE(eth_nWRITE),
 
 
 
                .eth_address(eth_address),
 
 
 
                .eth_data(eth_data),
 
 
 
                .eth_nBE(eth_nBE),
 
 
 
                .eth_reset(eth_reset)
 
 
 
);
 
 
 
 
 
 
 
//
 
// Instantiation of the UART16550
 
// Instantiation of the UART16550
 
//
 
//
 
uart_top uart_top (
 
uart_top uart_top (
 
 
 
 
 
        // WISHBONE common
 
        // WISHBONE common
Line 744... Line 788... 
        .ri_pad_i  ( 1'b0 ),
 
        .ri_pad_i  ( 1'b0 ),
 
        .dcd_pad_i ( 1'b0 )
 
        .dcd_pad_i ( 1'b0 )
 
);
 
);
 
 
 
 
 
//
 
//
 
// Coregen ROM (if implemented)
 
// ROM (if implemented)
 
//
 
//
 
/*rom rom (
 
/*rom rom (
 
        .addr(rom_address),
 
        .addr(rom_address),
 
        .clk(clk),
 
        .clk(clk),
 
        .dout(rom_data)
 
        .dout(rom_data)

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