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[/] [or1k_old/] [trunk/] [rc203soc/] [rtl/] [verilog/] [soc.v] - Diff between revs 1575 and 1587

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Rev 1575 Rev 1587
Line 41... Line 41... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.3  2005/09/16 00:39:03  jcastillo
 
 
 
// no message
 
 
 
//
 
// Revision 1.2  2005/05/26 12:25:01  jcastillo
 
// Revision 1.2  2005/05/26 12:25:01  jcastillo
 
// Added support for ethernet chip
 
// Added support for ethernet chip
 
//
 
//
 
// Revision 1.1.1.1  2004/12/13 17:14:31  jcastillo
 
// Revision 1.1.1.1  2004/12/13 17:14:31  jcastillo
 
// Firt import of OR1200 over Celoxica RC203 platform
 
// Firt import of OR1200 over Celoxica RC203 platform
Line 77... Line 80... 
 
 
 
 
module soc(
 
module soc(
 
   clk,reset,
 
   clk,reset,
 
 
 
 
 
   //SRAM Ports
 
   //SRAM Ports
 
   sram_nRW,sram_clk,sram_address,
 
   sram_nRW0,sram_clk0,sram_address0,
 
   sram_data,sram_nBW,sram_nCS,
 
   sram_data0,sram_nBW0,sram_nCS0,
 
 
 
 
 
 
 
   sram_nRW1,sram_clk1,sram_address1,
 
 
 
   sram_data1,sram_nBW1,sram_nCS1,
 
 
 
 
 
   //UART ports
 
   //UART ports
 
   uart_stx,uart_srx,
 
   uart_stx,uart_srx,
 
 
 
 
 
   //JTAG ports
 
   //JTAG ports
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   parameter ppic_ints = `OR1200_PIC_INTS;
 
   parameter ppic_ints = `OR1200_PIC_INTS;
 
 
 
 
 
   input         clk /* synthesis xc_clockbuftype = "BUFGDLL" */;
 
   input         clk /* synthesis xc_clockbuftype = "BUFGDLL" */;
 
   input         reset;
 
   input         reset;
 
 
 
 
 
   output        sram_nRW;
 
   output        sram_nRW0;
 
   output [19:0] sram_address;
 
   output [19:0] sram_address0;
 
   inout  [31:0] sram_data;
 
   inout  [31:0] sram_data0;
 
   output [3:0]  sram_nBW;
 
   output [3:0]  sram_nBW0;
 
   output        sram_nCS;
 
   output        sram_nCS0;
 
   output        sram_clk;
 
   output        sram_clk0;
 
 
 
 
 
 
 
   output        sram_nRW1;
 
 
 
   output [19:0] sram_address1;
 
 
 
   inout  [31:0] sram_data1;
 
 
 
   output [3:0]  sram_nBW1;
 
 
 
   output        sram_nCS1;
 
 
 
   output        sram_clk1;
 
 
 
 
 
   output        uart_stx;
 
   output        uart_stx;
 
   input         uart_srx;
 
   input         uart_srx;
 
 
 
 
 
   input         jtag_tdi;
 
   input         jtag_tdi;
Line 126... Line 139... 
   output [2:0]  eth_address;
 
   output [2:0]  eth_address;
 
   inout  [15:0] eth_data;   //INOUT
 
   inout  [15:0] eth_data;   //INOUT
 
   output [1:0]  eth_nBE;
 
   output [1:0]  eth_nBE;
 
   output        eth_reset;
 
   output        eth_reset;
 
 
 
 
 
assign sram_clk=clk;
 
assign sram_clk0=clk;
 
 
 
assign sram_clk1=clk;
 
 
 
 
 
//Declaring signals
 
//Declaring signals
 
wire    [1:0]             clmode;        // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
wire    [1:0]             clmode;        // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
wire    [ppic_ints-1:0]  pic_ints;
 
wire    [ppic_ints-1:0]  pic_ints;
 
 
 
 
Line 703... Line 717... 
        .wb_adr_i ( sram_wb_adr ),
 
        .wb_adr_i ( sram_wb_adr ),
 
        .wb_we_i  ( sram_wb_we ),
 
        .wb_we_i  ( sram_wb_we ),
 
        .wb_cyc_i ( sram_wb_cyc ),
 
        .wb_cyc_i ( sram_wb_cyc ),
 
        .wb_sel_i ( sram_wb_sel ),
 
        .wb_sel_i ( sram_wb_sel ),
 
 
 
 
 
        .nRW     ( sram_nRW ),
 
        .nRW0     ( sram_nRW0 ),
 
        .address ( sram_address ),
 
        .address0 ( sram_address0 ),
 
        .data    ( sram_data ),
 
        .data0    ( sram_data0 ),
 
        .nBW     ( sram_nBW ),
 
        .nBW0     ( sram_nBW0 ),
 
        .nCS     ( sram_nCS )
 
        .nCS0     ( sram_nCS0 ),
 
 
 
 
 
 
 
        .nRW1     ( sram_nRW1 ),
 
 
 
        .address1 ( sram_address1 ),
 
 
 
        .data1    ( sram_data1 ),
 
 
 
        .nBW1     ( sram_nBW1 ),
 
 
 
        .nCS1     ( sram_nCS1 )
 
);
 
);
 
 
 
 
 
//
 
//
 
// Instantiation of the ROM controller
 
// Instantiation of the ROM controller
 
//                           
//
Line 808... Line 828... 
   assign  pm_cpustall=0;
 
   assign  pm_cpustall=0;
 
   assign  rom_data=0;
 
   assign  rom_data=0;
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
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