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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2005/10/27 17:20:50 jcastillo
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// Supports two RAM banks by Jacob Bower
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//
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// Revision 1.3 2005/09/16 00:39:03 jcastillo
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// Revision 1.3 2005/09/16 00:39:03 jcastillo
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// no message
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// no message
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//
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//
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// Revision 1.2 2005/05/26 12:25:01 jcastillo
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// Revision 1.2 2005/05/26 12:25:01 jcastillo
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// Added support for ethernet chip
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// Added support for ethernet chip
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| Line 61... |
Line 64... |
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//
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//
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// Platform description
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// Platform description
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//
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//
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`define APP_INT_UART 2
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`define APP_INT_UART 2
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`define APP_INT_ETH 4
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`define APP_ADDR_DEC_W 8
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`define APP_ADDR_DEC_W 8
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`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
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`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
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`define APP_ADDR_FLASH `APP_ADDR_DEC_W'hf0
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`define APP_ADDR_FLASH `APP_ADDR_DEC_W'hf0
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`define APP_ADDR_DECP_W 4
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`define APP_ADDR_DECP_W 4
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`define APP_ADDR_PERIP `APP_ADDR_DEC_W'h9
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`define APP_ADDR_PERIP `APP_ADDR_DEC_W'h9
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Line 100... |
jtag_tdo,
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jtag_tdo,
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//Ethernet ports
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//Ethernet ports
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eth_nREAD,eth_nWRITE,
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eth_nREAD,eth_nWRITE,
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eth_address,eth_data,
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eth_address,eth_data,
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eth_nBE,eth_reset
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eth_nBE,eth_reset,eth_int
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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output eth_nWRITE;
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output eth_nWRITE;
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output [2:0] eth_address;
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output [2:0] eth_address;
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inout [15:0] eth_data; //INOUT
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inout [15:0] eth_data; //INOUT
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output [1:0] eth_nBE;
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output [1:0] eth_nBE;
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output eth_reset;
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output eth_reset;
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input eth_int;
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assign sram_clk0=clk;
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assign sram_clk0=clk;
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assign sram_clk1=clk;
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assign sram_clk1=clk;
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assign pic_ints[`APP_INT_ETH]=eth_int;
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//Declaring signals
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//Declaring signals
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wire [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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wire [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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wire [ppic_ints-1:0] pic_ints;
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wire [ppic_ints-1:0] pic_ints;
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//
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//
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