URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [drivers/] [serial/] [8250_early.c] - Diff between revs 3 and 7

Rev 3	Rev 7
Line 124...	Line 124...
`serial_out(port, UART_FCR, 0); /* no fifo */`	`serial_out(port, UART_FCR, 0); /* no fifo */`
`serial_out(port, UART_MCR, 0x3); /* DTR + RTS */`	`serial_out(port, UART_MCR, 0x3); /* DTR + RTS */`

`divisor = port->uartclk / (16 * device->baud);`	`divisor = port->uartclk / (16 * device->baud);`
`c = serial_in(port, UART_LCR);`	`c = serial_in(port, UART_LCR);`

`serial_out(port, UART_LCR, c \| UART_LCR_DLAB);`	`serial_out(port, UART_LCR, c \| UART_LCR_DLAB);`
`serial_out(port, UART_DLL, divisor & 0xff);`	`serial_out(port, UART_DLL, divisor & 0xff);`
`serial_out(port, UART_DLM, (divisor >> 8) & 0xff);`	`serial_out(port, UART_DLM, (divisor >> 8) & 0xff);`
`serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);`	`serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);`
`}`	`}`
Line 138...	Line 139...
`int mmio, length;`	`int mmio, length;`

`if (!options)`	`if (!options)`
`return -ENODEV;`	`return -ENODEV;`

`port->uartclk = BASE_BAUD * 16;`	`/* port->uartclk = BASE_BAUD * 16; */`
	`port->uartclk = SYS_CLK; /* changed */`

`if (!strncmp(options, "mmio,", 5)) {`	`if (!strncmp(options, "mmio,", 5)) {`
`port->iotype = UPIO_MEM;`	`port->iotype = UPIO_MEM;`
`port->mapbase = simple_strtoul(options + 5, &options, 0);`	`port->mapbase = simple_strtoul(options + 5, &options, 0);`
`#ifdef CONFIG_FIX_EARLYCON_MEM`	`#ifdef CONFIG_FIX_EARLYCON_MEM`
`set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, port->mapbase & PAGE_MASK);`	`set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, port->mapbase & PAGE_MASK);`