URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [include/] [asm-or32/] [board.h] - Diff between revs 7 and 9

Rev 7	Rev 9
Line 10...	Line 10...
`/* Memory organization */`	`/* Memory organization */`
`#define SRAM_BASE_ADD 0x00000000`	`#define SRAM_BASE_ADD 0x00000000`
`#define FLASH_BASE_ADD 0xf0000000`	`#define FLASH_BASE_ADD 0xf0000000`

`/* Devices base address */`	`/* Devices base address */`
`#define UART_BASE_ADD 0x90000000`	`#define UART_BASE_ADD 0x30000000`
`#define MC_BASE_ADD 0x93000000`	`#define MC_BASE_ADD 0x93000000`
`#define CRT_BASE_ADD 0x97000000`	`#define CRT_BASE_ADD 0x97000000`
`#define FBMEM_BASE_ADD 0xa8000000`	`#define FBMEM_BASE_ADD 0xa8000000`
`#define ETH_BASE_ADD 0x92000000`	`#define ETH_BASE_ADD 0x20000000`
`#define KBD_BASE_ADD 0x94000000`	`#define KBD_BASE_ADD 0x94000000`

`/* Define this if you want to use I and/or D cache */`	`/* Define this if you want to use I and/or D cache */`
`#define IC_SIZE CONFIG_OR32_IC_SIZE`	`#define IC_SIZE CONFIG_OR32_IC_SIZE`
`#define IC_LINE CONFIG_OR32_IC_LINE`	`#define IC_LINE CONFIG_OR32_IC_LINE`