| Line 12... |
Line 12... |
# Altera or its authorized distributors. Please refer to the
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# applicable agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# Quartus II: Generate Tcl File for Project
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# File: setup_prj.tcl
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# File: setup_prj.tcl
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# Generated on: Thu Nov 5 13:19:06 2009
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# Generated on: Sun Nov 29 16:35:34 2009
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# Load Quartus II Tcl Project package
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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package require ::quartus::project
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set need_to_close_project 0
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set need_to_close_project 0
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| Line 66... |
Line 66... |
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id or1k_soc_top
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "600 us" -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "600 us" -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or1k_soc_top_vlg_vec_tst -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or1k_soc_top_vlg_vec_tst -section_id or1k_soc_top
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
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set_global_assignment -name MISC_FILE /opt/workspace/xzeng/esig/trunk/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name MISC_FILE /opt/workspace/xzeng/esig/trunk/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.v -section_id or1k_soc_top
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| Line 271... |
Line 271... |
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
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set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
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set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
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set_global_assignment -name SEARCH_PATH "../../rtl/altera_ddr_ctrl/ddr_high_performance_controller-library"
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set_global_assignment -name SEARCH_PATH "../../rtl/altera_ddr_ctrl/ddr_high_performance_controller-library"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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set_location_assignment PIN_B9 -to wb_clk_pad_i
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set_location_assignment PIN_B9 -to wb_clk_pad_i
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set_location_assignment PIN_V9 -to ddr_pll_clk_pad_i
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set_location_assignment PIN_V9 -to ddr_pll_clk_pad_i
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set_location_assignment PIN_N2 -to rst_n_pad_i
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set_location_assignment PIN_N2 -to rst_n_pad_i
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set_location_assignment PIN_E18 -to uart_srx_pad_i
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set_location_assignment PIN_E18 -to uart_srx_pad_i
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set_location_assignment PIN_H17 -to uart_stx_pad_o
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set_location_assignment PIN_H17 -to uart_stx_pad_o
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