| Line 257... |
Line 257... |
set_global_assignment -name QIP_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.qip
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set_global_assignment -name QIP_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.qip
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set_global_assignment -name VHDL_FILE ../../rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
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set_global_assignment -name MISC_FILE /opt/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name MISC_FILE /opt/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE or1k_soc_top.vwf
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set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE or1k_soc_top.vwf
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set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE altera_ram.vwf
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set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE altera_ram.vwf
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set_global_assignment -name VHDL_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
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set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
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set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
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