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Line 1... |
/* adv_dbg_commands.c -- JTAG protocol bridge between GDB and Advanced debug module.
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/* adv_dbg_commands.c -- JTAG protocol bridge between GDB and Advanced debug module.
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Copyright(C) Nathan Yawn, nyawn@opencores.net
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Copyright (C) 2008-2010 Nathan Yawn, nyawn@opencores.net
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This file contains functions which perform high-level transactions
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This file contains functions which perform high-level transactions
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on a JTAG chain and debug unit, such as setting a value in the TAP IR
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on a JTAG chain and debug unit, such as setting a value in the TAP IR
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or doing a burst write through the wishbone module of the debug unit.
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or doing a burst write through the wishbone module of the debug unit.
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It uses the protocol for the Advanced Debug Interface (adv_dbg_if).
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It uses the protocol for the Advanced Debug Interface (adv_dbg_if).
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| Line 24... |
Line 24... |
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h> // for malloc()
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#include <stdlib.h> // for malloc()
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#include <unistd.h> // for exit()
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#include <unistd.h> // for exit()
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//#include <pthread.h> // for mutexes
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#include <strings.h> // for bzero()
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#include "chain_commands.h"
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#include "chain_commands.h"
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#include "adv_dbg_commands.h" // hardware-specific defines for the debug module
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#include "adv_dbg_commands.h" // hardware-specific defines for the debug module
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//#include "altera_virtual_jtag.h" // hardware-specifg defines for the Altera Virtual JTAG interface
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#include "cable_common.h" // low-level JTAG IO routines
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#include "cable_common.h" // low-level JTAG IO routines
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#include "errcodes.h"
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#include "errcodes.h"
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#define debug(...) //fprintf(stderr, __VA_ARGS__ )
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#define debug(...) //fprintf(stderr, __VA_ARGS__ )
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| Line 121... |
Line 120... |
return err;
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return err;
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debug("selreg %ld\n", regidx);
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debug("selreg %ld\n", regidx);
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// If this reg is already selected, don't do a JTAG transaction
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// If this reg is already selected, don't do a JTAG transaction
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if((current_chain >= 0) && (current_reg_idx[current_chain] == regidx))
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if(current_reg_idx[current_chain] == regidx)
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return APP_ERR_NONE;
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return APP_ERR_NONE;
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switch(current_chain) {
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switch(current_chain) {
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case DC_WISHBONE:
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case DC_WISHBONE:
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index_len = DBG_WB_REG_SEL_LEN;
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index_len = DBG_WB_REG_SEL_LEN;
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| Line 343... |
Line 342... |
uint32_t in_data;
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uint32_t in_data;
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unsigned long addr;
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unsigned long addr;
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uint32_t err_data[2];
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uint32_t err_data[2];
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int bus_error_retries = 0;
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int bus_error_retries = 0;
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int err = APP_ERR_NONE;
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int err = APP_ERR_NONE;
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static char *output_scratchpad = NULL;
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static int output_scratchpad_size = 0;
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debug("Doing burst read, word size %d, word count %d, start address 0x%lX", word_size_bytes, word_count, start_address);
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debug("Doing burst read, word size %d, word count %d, start address 0x%lX", word_size_bytes, word_count, start_address);
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if(word_count <= 0) {
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if(word_count <= 0) {
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debug("Ignoring illegal read burst length (%d)\n", word_count);
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debug("Ignoring illegal read burst length (%d)\n", word_count);
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| Line 395... |
Line 396... |
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// Send the BURST READ command, returns TAP to idle state
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// Send the BURST READ command, returns TAP to idle state
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if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
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if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
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return err;
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return err;
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// This is a kludge to word around oddities in the Xilinx BSCAN_* devices, and the
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// This is a kludge to work around oddities in the Xilinx BSCAN_* devices, and the
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// adv_dbg_if state machine. The debug FSM needs 1 TCK between UPDATE_DR above, and
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// adv_dbg_if state machine. The debug FSM needs 1 TCK between UPDATE_DR above, and
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// the CAPTURE_DR below, and the BSCAN_* won't provide it. So, we force it, by putting the TAP
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// the CAPTURE_DR below, and the BSCAN_* won't provide it. So, we force it, by putting the TAP
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// in BYPASS, which makes the debug_select line inactive, which is AND'ed with the TCK line (in the xilinx_internal_jtag module),
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// in BYPASS, which makes the debug_select line inactive, which is AND'ed with the TCK line (in the xilinx_internal_jtag module),
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// which forces it low. Then we re-enable USER1/debug_select to make TCK high. One TCK
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// which forces it low. Then we re-enable USER1/debug_select to make TCK high. One TCK
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// event, the hard way.
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// event, the hard way.
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Line 413... |
err |= tap_set_shift_dr();
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err |= tap_set_shift_dr();
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// We do not adjust for the DR length here. BYPASS regs are loaded with 0,
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// We do not adjust for the DR length here. BYPASS regs are loaded with 0,
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// and the debug unit waits for a '1' status bit before beginning to read data.
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// and the debug unit waits for a '1' status bit before beginning to read data.
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#ifdef ADBG_OPT_HISPEED
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// Get 1 status bit, then word_size_bytes*8 bits
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status = 0;
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j = 0;
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while(!status) { // Status indicates whether there is a word available to read. Wait until it returns true.
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err |= jtag_read_write_bit(0, &status);
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j++;
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// If max count exceeded, retry
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if(j > MAX_READ_STATUS_WAIT) {
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printf("Burst read timed out.\n");
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if(!retry_do()) {
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printf("Retry count exceeded in burst read!\n");
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return err|APP_ERR_MAX_RETRY;
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}
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err = APP_ERR_NONE; // on retry, errors cleared
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goto wb_burst_read_retry_full;
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}
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}
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// Check we have enough space for the (zero) output data
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if(output_scratchpad_size < (word_count*word_size_bytes))
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{
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free(output_scratchpad);
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output_scratchpad = (char *) malloc(word_count*word_size_bytes);
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if(output_scratchpad != NULL) {
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output_scratchpad_size = (word_count*word_size_bytes);
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bzero(output_scratchpad, output_scratchpad_size);
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}
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else {
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output_scratchpad_size = 0;
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return APP_ERR_MALLOC;
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}
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}
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//uint32_t outstream[64];
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//bzero((char *)outstream, 64*4);
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// Get the data in one shot
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err |= jtag_read_write_stream((uint32_t *)output_scratchpad, (uint32_t *)data, word_size_bits*word_count, 0, 0);
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for(i = 0; i < (word_count*word_size_bytes); i++)
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{
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crc_calc = adbg_compute_crc(crc_calc, ((uint8_t *)data)[i], 8);
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}
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#else
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// Repeat for each word: wait until ready = 1, then read word_size_bits bits.
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// Repeat for each word: wait until ready = 1, then read word_size_bits bits.
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for(; i < word_count; i++)
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for(; i < word_count; i++)
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{
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{
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// Get 1 status bit, then word_size_bytes*8 bits
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// Get 1 status bit, then word_size_bytes*8 bits
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status = 0;
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status = 0;
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Line 504... |
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if(word_size_bytes == 1) ((unsigned char *)data)[i] = in_data & 0xFF;
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if(word_size_bytes == 1) ((unsigned char *)data)[i] = in_data & 0xFF;
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else if(word_size_bytes == 2) ((unsigned short *)data)[i] = in_data & 0xFFFF;
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else if(word_size_bytes == 2) ((unsigned short *)data)[i] = in_data & 0xFFFF;
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else ((unsigned long *)data)[i] = in_data;
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else ((unsigned long *)data)[i] = in_data;
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}
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}
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#endif
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// All bus data was read. Read the data CRC from the debug module.
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// All bus data was read. Read the data CRC from the debug module.
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err |= jtag_read_write_stream(&out_data, &crc_read, 32, 0, 1);
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err |= jtag_read_write_stream(&out_data, &crc_read, 32, 0, 1);
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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err |= tap_exit_to_idle(); // Go from EXIT1 to IDLE
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Line 522... |
goto wb_burst_read_retry_full;
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goto wb_burst_read_retry_full;
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}
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}
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else debug("CRC OK!");
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else debug("CRC OK!");
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// Now, read the error register, and retry/recompute as necessary.
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// Now, read the error register, and retry/recompute as necessary.
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if(current_chain == DC_WISHBONE)
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if(current_chain == DC_WISHBONE)
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{
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{
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err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 1); // First, just get 1 bit...read address only if necessary,
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err |= adbg_ctrl_read(DBG_WB_REG_ERROR, err_data, 1); // First, just get 1 bit...read address only if necessary,
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if(err_data[0] & 0x1) { // Then we have a problem.
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if(err_data[0] & 0x1) { // Then we have a problem.
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| Line 506... |
Line 551... |
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// Set up and execute a burst write to a contiguous set of addresses
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// Set up and execute a burst write to a contiguous set of addresses
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int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address)
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int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address)
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{
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{
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unsigned char opcode;
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unsigned char opcode;
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uint8_t status;
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uint32_t datawords[2] = {0,0};
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uint32_t datawords[2] = {0,0};
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uint32_t statuswords[2] = {0,0};
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int i;
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int i;
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uint32_t crc_calc;
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uint32_t crc_calc;
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uint32_t crc_match;
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uint32_t crc_match;
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unsigned int word_size_bits;
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unsigned int word_size_bits;
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unsigned long addr;
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unsigned long addr;
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int bus_error_retries = 0;
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int bus_error_retries = 0;
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uint32_t err_data[2];
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uint32_t err_data[2];
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int loopct, successes;
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int loopct, successes;
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int first_status_loop;
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#ifndef ADBG_OPT_HISPEED
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uint8_t status;
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uint32_t statuswords[2] = {0,0};
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int first_status_loop = 1;
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#endif
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int err = APP_ERR_NONE;
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int err = APP_ERR_NONE;
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debug("Doing burst write, word size %d, word count %d, start address 0x%lx", word_size_bytes, word_count, start_address);
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debug("Doing burst write, word size %d, word count %d, start address 0x%lx\n", word_size_bytes, word_count, start_address);
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word_size_bits = word_size_bytes << 3;
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word_size_bits = word_size_bytes << 3;
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if(word_count <= 0) {
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if(word_count <= 0) {
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printf("Ignoring illegal burst write size (%d)\n", word_count);
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printf("Ignoring illegal burst write size (%d)\n", word_count);
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return 0;
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return 0;
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| Line 558... |
Line 605... |
default:
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default:
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printf("ERROR! Illegal debug chain selected while doing burst WRITE!\n");
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printf("ERROR! Illegal debug chain selected while doing burst WRITE!\n");
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return 1;
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return 1;
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}
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}
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#ifndef ADBG_OPT_HISPEED
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// Compute which loop iteration in which to expect the first status bit
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// Compute which loop iteration in which to expect the first status bit
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first_status_loop = 1 + ((global_DR_prefix_bits + global_DR_postfix_bits)/(word_size_bits+1));
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first_status_loop = 1 + ((global_DR_prefix_bits + global_DR_postfix_bits)/(word_size_bits+1));
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#endif
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wb_burst_write_retry_full:
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wb_burst_write_retry_full:
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i = 0;
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i = 0;
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addr = start_address;
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addr = start_address;
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wb_burst_write_retry_partial:
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wb_burst_write_retry_partial:
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| Line 574... |
Line 623... |
// Send burst command, return to idle state
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// Send burst command, return to idle state
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if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
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if(err |= adbg_burst_command(opcode, addr, (word_count-i))) // word_count-i in case of partial retry
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return err;
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return err;
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// Get us back to shift_dr mode to write a burst
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// Get us back to shift_dr mode to write a burst
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//err |= jtag_write_bit(TMS); // select_dr_scan
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//err |= jtag_write_bit(0); // capture_ir
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//err |= jtag_write_bit(0); // shift_ir
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err |= tap_set_shift_dr();
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err |= tap_set_shift_dr();
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// Write a start bit (a 1) so it knows when to start counting
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// Write a start bit (a 1) so it knows when to start counting
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err |= jtag_write_bit(TDO);
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err |= jtag_write_bit(TDO);
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#ifdef ADBG_OPT_HISPEED
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// If compiled for "hi-speed" mode, we don't read a status bit after every
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// word written. This saves a lot of complication!
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// In this case, the loop below is used only for CRC calculation.
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err |= jtag_write_stream((uint32_t *) data, (word_count*word_size_bits), 0); // Write data
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#endif
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// Now, repeat...
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// Now, repeat...
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for(loopct = 0; i < word_count; i++,loopct++) // loopct only used to check status...
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for(loopct = 0; i < word_count; i++,loopct++) // loopct only used to check status...
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{
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{
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// Write word_size_bytes*8 bits, then get 1 status bit
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// Write word_size_bytes*8 bits, then get 1 status bit
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if(word_size_bytes == 4) datawords[0] = ((unsigned long *)data)[i];
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if(word_size_bytes == 4) datawords[0] = ((unsigned long *)data)[i];
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else if(word_size_bytes == 2) datawords[0] = ((unsigned short *)data)[i];
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else if(word_size_bytes == 2) datawords[0] = ((unsigned short *)data)[i];
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else datawords[0] = ((unsigned char *)data)[i];
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else datawords[0] = ((unsigned char *)data)[i];
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crc_calc = adbg_compute_crc(crc_calc, datawords[0], word_size_bits);
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crc_calc = adbg_compute_crc(crc_calc, datawords[0], word_size_bits);
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#ifndef ADBG_OPT_HISPEED
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// This is an optimization
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// This is an optimization
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if((global_DR_prefix_bits + global_DR_postfix_bits) == 0) {
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if((global_DR_prefix_bits + global_DR_postfix_bits) == 0) {
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//#endif
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err |= jtag_write_stream(datawords, word_size_bits, 0); // Write data
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err |= jtag_write_stream(datawords, word_size_bits, 0); // Write data
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//#ifndef ADBG_OPT_HISPEED
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err |= jtag_read_write_bit(0, &status); // Read status bit
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err |= jtag_read_write_bit(0, &status); // Read status bit
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if(!status) {
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if(!status) {
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addr = start_address + (i*word_size_bytes);
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addr = start_address + (i*word_size_bytes);
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printf("Write before bus ready, retrying (idx %i, addr 0x%08lX).\n", i, addr);
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printf("Write before bus ready, retrying (idx %i, addr 0x%08lX).\n", i, addr);
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if(!retry_do()) { printf("Retry count exceeded! Abort!\n\n"); exit(1);}
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if(!retry_do()) { printf("Retry count exceeded! Abort!\n\n"); exit(1);}
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| Line 620... |
Line 676... |
// Don't bother going to TAP idle state, we're about to reset the TAP
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// Don't bother going to TAP idle state, we're about to reset the TAP
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goto wb_burst_write_retry_partial;
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goto wb_burst_write_retry_partial;
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}
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}
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}
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}
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}
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}
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#endif
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if(err) {
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if(err) {
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printf("Error %s getting status bit, retrying.\n", get_err_string(err));
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printf("Error %s during burst write, retrying.\n", get_err_string(err));
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if(!retry_do()) {
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if(!retry_do()) {
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printf("Retry count exceeded!\n");
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printf("Retry count exceeded!\n");
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return err|APP_ERR_MAX_RETRY;
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return err|APP_ERR_MAX_RETRY;
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}
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}
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err = APP_ERR_NONE;
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err = APP_ERR_NONE;
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| Line 636... |
Line 693... |
}
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}
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debug("Wrote 0x%0lx", datawords[0]);
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debug("Wrote 0x%0lx", datawords[0]);
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}
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}
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// *** If this is a multi-device chain, at least one status bit will be lost.
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// *** If this is a multi-device chain (and we're not in hi-speed mode), at least one status bit will be lost.
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// *** If we want to check for it, we'd have to look while sending the CRC, and
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// *** If we want to check for it, we'd have to look while sending the CRC, and
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// *** maybe while burning bits to get the match bit. So, for now, there is a
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// *** maybe while burning bits to get the match bit. So, for now, there is a
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// *** hole here.
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// *** hole here.
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// Done sending data, Send the CRC we computed
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// Done sending data, Send the CRC we computed
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