URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sw/] [adv_jtag_bridge/] [sim_rtl/] [dbg_comm.v] - Diff between revs 12 and 21

Rev 12	Rev 21
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: dbg_comm.v,v $`	`// $Log: dbg_comm.v,v $`
`// Revision 1.3 2009/05/17 20:55:57 Nathan`	`// Revision 1.3 2009-05-17 20:55:57 Nathan`
`// Changed email address to opencores.org`	`// Changed email address to opencores.org`
`//`	`//`
`// Revision 1.2 2008/07/22 18:23:25 Nathan`	`// Revision 1.2 2008/07/22 18:23:25 Nathan`
`// Added clock and reset outputs to make simulation system simpler. Fixed P_TRST signal name. Added fflush calls to make file IO work as quickly as possible. Write the data out bit on falling clock edge. Cleanup.`	`// Added clock and reset outputs to make simulation system simpler. Fixed P_TRST signal name. Added fflush calls to make file IO work as quickly as possible. Write the data out bit on falling clock edge. Cleanup.`
`//`	`//`