| Line 51... |
Line 51... |
// Constants - do not override.
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// Constants - do not override.
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parameter TX_IDLE = 0;
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parameter TX_IDLE = 0;
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parameter TX_SENDING = 1;
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parameter TX_SENDING = 1;
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parameter TX_DELAY_RESTART = 2;
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parameter TX_DELAY_RESTART = 2;
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reg [10:0] clk_divider = CLOCK_DIVIDE;
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reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
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reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
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reg [2:0] recv_state = RX_IDLE;
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reg [2:0] recv_state = RX_IDLE;
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reg [5:0] rx_countdown;
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reg [5:0] rx_countdown;
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reg [3:0] rx_bits_remaining;
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reg [3:0] rx_bits_remaining;
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reg [7:0] rx_data;
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reg [7:0] rx_data;
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| Line 83... |
Line 84... |
// The clk_divider counter counts down from
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// The clk_divider counter counts down from
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// the CLOCK_DIVIDE constant. Whenever it
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// the CLOCK_DIVIDE constant. Whenever it
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// reaches 0, 1/16 of the bit period has elapsed.
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// reaches 0, 1/16 of the bit period has elapsed.
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// Countdown timers for the receiving and transmitting
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// Countdown timers for the receiving and transmitting
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// state machines are decremented.
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// state machines are decremented.
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clk_divider = clk_divider - 1;
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rx_clk_divider = rx_clk_divider - 1;
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if (!clk_divider) begin
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if (!rx_clk_divider) begin
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clk_divider = CLOCK_DIVIDE;
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rx_clk_divider = CLOCK_DIVIDE;
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rx_countdown = rx_countdown - 1;
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rx_countdown = rx_countdown - 1;
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end
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tx_clk_divider = tx_clk_divider - 1;
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if (!tx_clk_divider) begin
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tx_clk_divider = CLOCK_DIVIDE;
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tx_countdown = tx_countdown - 1;
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tx_countdown = tx_countdown - 1;
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end
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end
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// Receive state machine
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// Receive state machine
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case (recv_state)
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case (recv_state)
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| Line 98... |
Line 103... |
// A low pulse on the receive line indicates the
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// A low pulse on the receive line indicates the
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// start of data.
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// start of data.
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if (!rx) begin
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if (!rx) begin
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// Wait half the period - should resume in the
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// Wait half the period - should resume in the
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// middle of this first pulse.
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// middle of this first pulse.
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rx_clk_divider = CLOCK_DIVIDE;
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rx_countdown = 8;
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rx_countdown = 8;
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recv_state = RX_CHECK_START;
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recv_state = RX_CHECK_START;
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end
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end
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end
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end
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RX_CHECK_START: begin
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RX_CHECK_START: begin
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| Line 176... |
Line 182... |
// state, start transmitting the current content
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// state, start transmitting the current content
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// of the tx_byte input.
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// of the tx_byte input.
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tx_data = tx_byte;
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tx_data = tx_byte;
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// Send the initial, low pulse of 1 bit period
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// Send the initial, low pulse of 1 bit period
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// to signal the start, followed by the data
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// to signal the start, followed by the data
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tx_clk_divider = CLOCK_DIVIDE;
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tx_countdown = 16;
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tx_countdown = 16;
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tx_out = 0;
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tx_out = 0;
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tx_bits_remaining = 8;
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tx_bits_remaining = 8;
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tx_state = TX_SENDING;
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tx_state = TX_SENDING;
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end
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end
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