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-- Company:
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-- Engineer: Joao Carlos Nunes Bittencourt
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-- Engineer:
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----------------------------------------------------------------------------------
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--
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-- Create Date: 13:18:18 03/06/2012
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-- Create Date: 21:48:33 04/18/2012
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----------------------------------------------------------------------------------
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-- Design Name:
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-- Design Name: Adder Macrofunction
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-- Module Name: adder - Behavioral
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-- Module Name: adder - behavioral
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-- Project Name:
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-- Target Devices:
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-- Project Name: 16-bit uRISC Processor
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- 1.0 - File Created
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-- Additional Comments:
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-- 2.0 - Project refactoring
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity adder is
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entity adder is
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Generic (
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Generic (
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WIDTH : integer := 16 );
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WIDTH : integer := 16 );
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Port (
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Port (
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data_a : in std_logic_vector (WIDTH-1 downto 0);
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sink_a : in std_logic_vector (WIDTH-1 downto 0);
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data_b : in std_logic_vector (WIDTH-1 downto 0);
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sink_b : in std_logic_vector (WIDTH-1 downto 0);
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result : out std_logic_vector (WIDTH-1 downto 0) );
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src_data : out std_logic_vector (WIDTH-1 downto 0) );
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end adder;
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end adder;
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architecture Macrofunction of adder is
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architecture behavioral of adder is
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begin
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begin
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process(data_a, data_b)
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process(sink_a, sink_b)
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variable mAux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);
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variable aux : std_logic_vector(WIDTH-1 downto 0) := conv_std_logic_vector(0,WIDTH);
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begin
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begin
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mAux := data_a + data_b;
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aux := sink_a + sink_b;
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result <= mAux;
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src_data <= aux;
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end process;
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end process;
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end Macrofunction;
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end behavioral;
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