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-- Company:
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-- Engineer: Joao Carlos Nunes Bittencourt
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-- Engineer:
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--
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-- Create Date: 13:18:18 03/06/2012
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-- Create Date: 01:14:05 05/02/2012
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-- Design Name:
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-- Design Name: D-Flip-flop
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-- Module Name: DFF - FlipFlop
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-- Module Name: dff - behavioral
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-- Project Name:
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-- Target Devices:
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-- Project Name: 16-bit uRISC Processor
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- 1.0 - File Created
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-- Additional Comments:
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-- 2.0 - Project refactoring
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity dff is
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entity dff is
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Generic (WIDTH : integer := 16);
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generic( WIDTH : integer := 16 );
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Port ( clk : in std_logic;
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port ( clk : in std_logic;
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en : in std_logic;
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enable : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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D : in std_logic_vector (WIDTH-1 downto 0);
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sink_d : in std_logic_vector (WIDTH-1 downto 0);
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Q : out std_logic_vector (WIDTH-1 downto 0));
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src_q : out std_logic_vector (WIDTH-1 downto 0)
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);
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end dff;
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end dff;
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architecture FlipFlop of dff is
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architecture behavioral of dff is
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begin
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begin
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process (clock,reset)
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process (clock,reset)
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begin
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begin
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if(reset = '0') then
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if(reset = '0') then
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Q <= (others => '0');
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src_q <= (others => '0');
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if(enable = '1') then
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if(enable = '1') then
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Q <= D;
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src_q <= sink_d;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end FlipFlop;
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end behavioral;
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