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[/] [ourisc/] [trunk/] [rtl/] [common/] [mux2x1.vhd] - Diff between revs 2 and 6
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Rev 6 |
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity mux2x1 is
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entity mux2x1 is
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Generic ( WIDTH : integer := 16 );
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generic ( WIDTH : integer := 16 );
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Port ( in_a : in std_logic_vector (WIDTH-1 downto 0);
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port ( sink_a : in std_logic_vector (WIDTH-1 downto 0);
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in_b : in std_logic_vector (WIDTH-1 downto 0);
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sink_b : in std_logic_vector (WIDTH-1 downto 0);
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sel : in std_logic_vector (0 downto 0); -- FIXME
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sink_sel : in std_logic_vector (0 downto 0); -- FIXME
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dataout : out std_logic_vector (WIDTH-1 downto 0));
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src_data : out std_logic_vector (WIDTH-1 downto 0)
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);
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end mux2x1;
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end mux2x1;
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architecture Primitive of mux2x1 is
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architecture Primitive of mux2x1 is
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begin
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begin
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process(sel, in_a, in_b)
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process(sink_sel, sink_a, sink_b)
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begin
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begin
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case sel is
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case sink_sel is
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when "0" => dataout <= in_a;
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when "0" => src_data <= sink_a;
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when "1" => dataout <= in_b;
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when "1" => src_data <= sink_b;
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when others => dataout <= (others => '0');
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when others => src_data <= (others => '0');
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end case;
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end case;
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end process;
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end process;
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end Primitive;
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end Primitive;
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