URL
https://opencores.org/ocsvn/ourisc/ourisc/trunk
[/] [ourisc/] [trunk/] [rtl/] [common/] [mux2x1.vhd] - Diff between revs 2 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 19... |
Line 19... |
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
entity mux2x1 is
|
entity mux2x1 is
|
Generic ( WIDTH : integer := 16 );
|
generic ( WIDTH : integer := 16 );
|
Port ( in_a : in std_logic_vector (WIDTH-1 downto 0);
|
port ( sink_a : in std_logic_vector (WIDTH-1 downto 0);
|
in_b : in std_logic_vector (WIDTH-1 downto 0);
|
sink_b : in std_logic_vector (WIDTH-1 downto 0);
|
sel : in std_logic_vector (0 downto 0); -- FIXME
|
sink_sel : in std_logic_vector (0 downto 0); -- FIXME
|
dataout : out std_logic_vector (WIDTH-1 downto 0));
|
src_data : out std_logic_vector (WIDTH-1 downto 0)
|
|
);
|
end mux2x1;
|
end mux2x1;
|
|
|
architecture Primitive of mux2x1 is
|
architecture Primitive of mux2x1 is
|
begin
|
begin
|
process(sel, in_a, in_b)
|
process(sink_sel, sink_a, sink_b)
|
begin
|
begin
|
case sel is
|
case sink_sel is
|
when "0" => dataout <= in_a;
|
when "0" => src_data <= sink_a;
|
when "1" => dataout <= in_b;
|
when "1" => src_data <= sink_b;
|
when others => dataout <= (others => '0');
|
when others => src_data <= (others => '0');
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
end Primitive;
|
end Primitive;
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.