URL
https://opencores.org/ocsvn/ourisc/ourisc/trunk
[/] [ourisc/] [trunk/] [rtl/] [common/] [mux4x1.vhd] - Diff between revs 2 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 22... |
Line 22... |
|
|
entity mux4x1 is
|
entity mux4x1 is
|
generic (
|
generic (
|
WIDTH : integer := 16 );
|
WIDTH : integer := 16 );
|
port (
|
port (
|
in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
|
sink_a : in std_logic_vector (WIDTH-1 downto 0);
|
in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
|
sink_b : in std_logic_vector (WIDTH-1 downto 0);
|
in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
|
sink_c : in std_logic_vector (WIDTH-1 downto 0);
|
in_d : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
|
sink_d : in std_logic_vector (WIDTH-1 downto 0);
|
sel : in STD_LOGIC_VECTOR (1 downto 0);
|
sink_sel : in std_logic_vector (1 downto 0);
|
dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) );
|
src_data : out std_logic_vector (WIDTH-1 downto 0) );
|
end mux4x1;
|
end mux4x1;
|
|
|
architecture Multiplex of mux4x1 is
|
architecture Multiplex of mux4x1 is
|
begin
|
begin
|
process(sel, in_a, in_b, in_c)
|
process(sink_sel, sink_a, sink_b, sink_c)
|
begin
|
begin
|
case sel is
|
case sink_sel is
|
when "00" => dataout <= in_a;
|
when "00" => src_data <= sink_a;
|
when "01" => dataout <= in_b;
|
when "01" => src_data <= sink_b;
|
when "10" => dataout <= in_c;
|
when "10" => src_data <= sink_c;
|
when "11" => dataout <= in_d;
|
when "11" => src_data <= sink_d;
|
when others => dataout <= (others => '0');
|
when others => src_data <= (others => '0');
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end Multiplex;
|
end Multiplex;
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.