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[/] [ourisc/] [trunk/] [rtl/] [common/] [mux4x1.vhd] - Diff between revs 2 and 6
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Rev 6 |
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Line 22... |
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entity mux4x1 is
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entity mux4x1 is
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generic (
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generic (
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WIDTH : integer := 16 );
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WIDTH : integer := 16 );
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port (
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port (
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in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
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sink_a : in std_logic_vector (WIDTH-1 downto 0);
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in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
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sink_b : in std_logic_vector (WIDTH-1 downto 0);
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in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
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sink_c : in std_logic_vector (WIDTH-1 downto 0);
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in_d : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
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sink_d : in std_logic_vector (WIDTH-1 downto 0);
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sel : in STD_LOGIC_VECTOR (1 downto 0);
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sink_sel : in std_logic_vector (1 downto 0);
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dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) );
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src_data : out std_logic_vector (WIDTH-1 downto 0) );
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end mux4x1;
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end mux4x1;
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architecture Multiplex of mux4x1 is
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architecture Multiplex of mux4x1 is
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begin
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begin
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process(sel, in_a, in_b, in_c)
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process(sink_sel, sink_a, sink_b, sink_c)
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begin
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begin
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case sel is
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case sink_sel is
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when "00" => dataout <= in_a;
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when "00" => src_data <= sink_a;
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when "01" => dataout <= in_b;
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when "01" => src_data <= sink_b;
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when "10" => dataout <= in_c;
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when "10" => src_data <= sink_c;
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when "11" => dataout <= in_d;
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when "11" => src_data <= sink_d;
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when others => dataout <= (others => '0');
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when others => src_data <= (others => '0');
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end case;
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end case;
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end process;
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end process;
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end Multiplex;
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end Multiplex;
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