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[/] [ourisc/] [trunk/] [rtl/] [pc_adder.vhd] - Diff between revs 7 and 8
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-- Engineer: Joao Carlos Nunes Bittencourt
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-- Create Date: 13:18:18 03/06/2012
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-- Design Name: Program Counter Adder
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-- Module Name: pc_adder - behavioral
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-- Project Name: 16-bit uRISC Processor
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-- Revision:
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-- 1.0 - File Created
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-- 2.0 - Project refactoring
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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