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module f32m_mult(clk, reset, a, b, c, done);
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module f32m_mult(clk, reset, a, b, c, done);
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input reset, clk;
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input reset, clk;
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input [`W2:0] a, b;
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input [`W2:0] a, b;
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output reg [`W2:0] c;
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output reg [`W2:0] c;
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output reg done;
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output reg done;
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wire [`WIDTH:0] a0,a1,b0,b1,
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wire [`WIDTH:0] a0,a1,b0,b1,c0,c1,
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v1,v2,v6,
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v1,v2,v3,v4,v5,v6;
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c0,c1,
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in1,in2,o;
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reg [`WIDTH:0] v3,v4,v5;
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reg [3:0] K;
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wire load1, load2, load3, set1, set2, set3;
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reg mult_reset;
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reg mult_reset;
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wire mult_done;
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wire mult_done, p;
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reg delay1, delay2;
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wire delay3;
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wire rst;
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assign rst = delay2;
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assign {a1,a0} = a;
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assign {a1,a0} = a;
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assign {b1,b0} = b;
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assign {b1,b0} = b;
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assign {load1,load2,load3} = K[3:1];
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assign {set1,set2,set3} = K[3:1];
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f3m_add
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f3m_add
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ins1 (a0, a1, v1), // v1 == a0 + a1
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ins1 (a0, a1, v1), // v1 == a0 + a1
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ins2 (b0, b1, v2), // v2 == b0 + b1
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ins2 (b0, b1, v2), // v2 == b0 + b1
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ins3 (v3, v4, v6); // v6 == v3 + v4 = a0*b0 + a1*b1
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ins3 (v3, v4, v6); // v6 == v3 + v4 = a0*b0 + a1*b1
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f3m_sub
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f3m_sub
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ins7 (v5, v6, c1), // c1 == v5 - v6 = (a0+a1) * (b0+b1) - (a0*b0 + a1*b1)
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ins7 (v5, v6, c1), // c1 == v5 - v6 = (a0+a1) * (b0+b1) - (a0*b0 + a1*b1)
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ins8 (v3, v4, c0); // c0 == a0*b0 - a1*b1
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ins8 (v3, v4, c0); // c0 == a0*b0 - a1*b1
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// only one $f3m_mult$ module doing three multiplication
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// v3 == a0 * b0
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// v3 == a0 * b0
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// v4 == a1 * b1
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// v4 == a1 * b1
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// v5 == v1 * v2 = (a0+a1) * (b0+b1)
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// v5 == v1 * v2 = (a0+a1) * (b0+b1)
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f3m_mux3
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f3m_mult3
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ins9 (a0, load1, a1, load2, v1, load3, in1),
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ins9 (clk, mult_reset, a0, b0, v3, a1, b1, v4, v1, v2, v5, mult_done);
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ins10 (b0, load1, b1, load2, v2, load3, in2);
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f3m_mult
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ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
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func6
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func6
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ins12 (clk, mult_done, delay3);
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ins10 (clk, mult_done, p);
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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mult_reset <= reset;
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if (set1) begin v3 <= o; end
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if (set2) begin v4 <= o; end
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if (set3) begin v5 <= o; end
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end
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always @ (posedge clk)
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begin
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if (reset) K <= 4'b1000;
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else if (delay3) K <= {1'b0,K[3:1]}; // wait for Mr. Comb. Logic :)
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end
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always @ (posedge clk)
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begin
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if (rst) mult_reset <= 1; // wait for Mr. Comb. Logic :)
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else if (mult_done) mult_reset <= 1;
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else mult_reset <= 0;
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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done <= 0;
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done <= 0;
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else if (K[0])
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else if (p)
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begin
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begin
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done <= 1; c <= {c1, c0};
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done <= 1; c <= {c1, c0};
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end
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end
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always @ (posedge clk)
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begin
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delay2 <= delay1; delay1 <= reset;
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end
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endmodule
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endmodule
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// C == A^3 in GF(3^{2m})
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// C == A^3 in GF(3^{2m})
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module f32m_cubic(clk, a, c);
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module f32m_cubic(clk, a, c);
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input clk;
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input clk;
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