| Line 19... |
Line 19... |
e3, e4, e5,
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e3, e4, e5,
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mult_done, p, rst;
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mult_done, p, rst;
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wire [`W2:0] in0, in1;
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wire [`W2:0] in0, in1;
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wire [`W2:0] o;
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wire [`W2:0] o;
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reg mult_reset, delay1, delay2;
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reg mult_reset, delay1, delay2;
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reg [`W2:0] in0d,in1d;
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assign {e0,e1,e2,e3,e4,e5} = K[6:1];
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assign {e0,e1,e2,e3,e4,e5} = K[6:1];
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assign {a2,a1,a0} = a;
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assign {a2,a1,a0} = a;
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assign {b2,b1,b0} = b;
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assign {b2,b1,b0} = b;
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assign d4 = x0;
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assign d4 = x0;
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| Line 31... |
Line 32... |
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f32m_mux6
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f32m_mux6
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ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
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f32m_mult
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f32m_mult
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ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
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ins3 (clk, mult_reset, in0d, in1d, o, mult_done); // o == in0 * in1
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func6
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func6
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ins4 (clk, reset, mult_done, p);
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ins4 (clk, reset, mult_done, p);
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f32m_add
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f32m_add
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins5 (a1, a2, v1), // v1 == a1+a2
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ins6 (b1, b2, v2), // v2 == b1+b2
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ins6 (b1, b2, v2), // v2 == b1+b2
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| Line 56... |
Line 57... |
f32m_add4
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f32m_add4
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ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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in0d <= in0; in1d <= in1;
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end
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always @ (posedge clk)
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begin
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if (reset) K <= 7'b1000000;
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if (reset) K <= 7'b1000000;
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else if (p | K[0]) K <= {1'b0,K[6:1]};
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else if (p | K[0]) K <= {1'b0,K[6:1]};
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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