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Line 88... |
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// do Tate pairing, hahahaha
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// do Tate pairing, hahahaha
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module tate_pairing(clk, reset, x1, y1, x2, y2, done, sel, out);
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module tate_pairing(clk, reset, x1, y1, x2, y2, done, sel, out);
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input clk, reset;
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input clk, reset;
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input [`WIDTH:0] x1, y1, x2, y2;
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input [`WIDTH:0] x1, y1, x2, y2;
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input [2:0] sel;
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input [7:0] sel;
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output reg done;
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output reg done;
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output reg [149:0] out;
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output reg [149:0] out;
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reg delay1, rst1;
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reg delay1, rst1;
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wire done1, rst2;
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wire done1, rst2;
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Line 125... |
always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0]) begin done <= 1; o <= out2; end
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else if (K[0]) begin done <= 1; o <= out2; end
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always @ (o, sel)
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always @ (o, sel)
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case (sel)
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out = (sel[0] ? o[150-1:0] : 0) |
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3'd0: out = o[150-1:0];
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(sel[1] ? o[300-1:150] : 0) |
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3'd1: out = o[300-1:150];
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(sel[2] ? o[450-1:300] : 0) |
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3'd2: out = o[450-1:300];
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(sel[3] ? o[600-1:450] : 0) |
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3'd3: out = o[600-1:450];
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(sel[4] ? o[750-1:600] : 0) |
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3'd4: out = o[750-1:600];
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(sel[5] ? o[900-1:750] : 0) |
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3'd5: out = o[900-1:750];
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(sel[6] ? o[1050-1:900] : 0) |
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3'd6: out = o[1050-1:900];
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(sel[7] ? o[`W6-1:1050] : 0) ;
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3'd7: out = o[`W6-1:1050];
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default: out = 0;
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endcase
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endmodule
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endmodule
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