| Line 95... |
Line 95... |
output reg [149:0] out;
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output reg [149:0] out;
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reg delay1, rst1;
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reg delay1, rst1;
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wire done1, rst2;
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wire done1, rst2;
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wire [`W6:0] out1, out2;
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wire [`W6:0] out1, out2;
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wire [149:0] tmp;
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reg [`W6:0] o;
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reg [`W6:0] o;
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reg [2:0] K;
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reg [2:0] K;
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assign tmp = o[`W6:1050];
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duursma_lee_algo
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duursma_lee_algo
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ins1 (clk, rst1, x1, y1, x2, y2, done1, out1);
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ins1 (clk, rst1, x1, y1, x2, y2, done1, out1);
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second_part
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second_part
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ins2 (clk, rst2, out1, out2, done2);
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ins2 (clk, rst2, out1, out2, done2);
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func6
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func6
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| Line 124... |
Line 127... |
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0]) begin done <= 1; o <= out2; end
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else if (K[0]) begin done <= 1; o <= out2; end
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always @ (o, sel)
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always @ (o, sel, tmp)
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out = (sel[0] ? o[150-1:0] : 0) |
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out = (sel[0] ? o[150-1:0] : 0) |
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(sel[1] ? o[300-1:150] : 0) |
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(sel[1] ? o[300-1:150] : 0) |
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(sel[2] ? o[450-1:300] : 0) |
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(sel[2] ? o[450-1:300] : 0) |
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(sel[3] ? o[600-1:450] : 0) |
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(sel[3] ? o[600-1:450] : 0) |
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(sel[4] ? o[750-1:600] : 0) |
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(sel[4] ? o[750-1:600] : 0) |
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(sel[5] ? o[900-1:750] : 0) |
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(sel[5] ? o[900-1:750] : 0) |
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(sel[6] ? o[1050-1:900] : 0) |
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(sel[6] ? o[1050-1:900] : 0) |
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(sel[7] ? o[`W6-1:1050] : 0) ;
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(sel[7] ? tmp : 0) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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