| Line 5... |
Line 5... |
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// Inputs
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// Inputs
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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reg [`WIDTH:0] x1, y1, x2, y2;
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reg [`WIDTH:0] x1, y1, x2, y2;
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reg [2:0] sel;
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reg [7:0] sel;
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reg [149:0] o0,o1,o2,o3,o4,o5,o6,o7;
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reg [149:0] o0,o1,o2,o3,o4,o5,o6,o7;
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reg [`W6:0] wish;
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reg [`W6:0] wish;
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wire [`W6:0] o;
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assign o = {o7[113:0],o6,o5,o4,o3,o2,o1,o0};
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// Outputs
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// Outputs
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wire done;
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wire done;
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wire [149:0] out;
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wire [149:0] out;
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| Line 59... |
Line 56... |
y2 = 194'h8481099460280628960a82559920000a99a2106955289a40;
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y2 = 194'h8481099460280628960a82559920000a99a2106955289a40;
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wish = {{194'h148a60225a14a81189aa09a22848104418aa6505801246205,194'h520094820010a12551069915258a58848501052005a85609},{194'ha484046591204499252009806480198a2549624a5181695,194'h21905848428558a806805a4518844049651812a88955a8868},{194'h5565059245921805891121a95a6949564201a2a068910558,194'ha6298884510610298462582969269a122260a05a8241055a}};
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wish = {{194'h148a60225a14a81189aa09a22848104418aa6505801246205,194'h520094820010a12551069915258a58848501052005a85609},{194'ha484046591204499252009806480198a2549624a5181695,194'h21905848428558a806805a4518844049651812a88955a8868},{194'h5565059245921805891121a95a6949564201a2a068910558,194'ha6298884510610298462582969269a122260a05a8241055a}};
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 0;
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@ (negedge clk); reset = 0;
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@ (posedge done); @ (negedge clk);
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@ (posedge done); @ (negedge clk);
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sel = 0; #20; o0=out;
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sel = 8'b0000_0001; #20; o0=out;
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sel = 1; #20; o1=out;
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sel = 8'b0000_0010; #20; o1=out;
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sel = 2; #20; o2=out;
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sel = 8'b0000_0100; #20; o2=out;
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sel = 3; #20; o3=out;
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sel = 8'b0000_1000; #20; o3=out;
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sel = 4; #20; o4=out;
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sel = 8'b0001_0000; #20; o4=out;
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sel = 5; #20; o5=out;
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sel = 8'b0010_0000; #20; o5=out;
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sel = 6; #20; o6=out;
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sel = 8'b0100_0000; #20; o6=out;
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sel = 7; #20; o7=out;
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sel = 8'b1000_0000; #20; o7=out;
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if (o !== wish) $display("E");
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if ({o7[113:0],o6,o5,o4,o3,o2,o1,o0} !== wish) begin $display("E"); end
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$finish;
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$finish;
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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endmodule
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endmodule
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