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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/10/17 09:11:52 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.12 2003/08/21 20:49:03 tadejm
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// Revision 1.12 2003/08/21 20:49:03 tadejm
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// Added signals for WB Master B3.
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// Added signals for WB Master B3.
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//
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//
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// Revision 1.11 2003/08/08 16:36:33 tadejm
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// Revision 1.11 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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BIST debug chain port signals
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BIST debug chain port signals
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-----------------------------------------------------*/
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-----------------------------------------------------*/
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input mbist_si_i; // bist scan serial in
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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output mbist_so_o; // bist scan serial out
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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// internal wires for serial chain connection
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wire SO_internal ;
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wire SI_internal = SO_internal ;
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`endif
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`endif
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// declare clock and reset wires
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// declare clock and reset wires
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wire pci_clk = pci_clk_i ;
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wire pci_clk = pci_clk_i ;
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wire wb_clk = wb_clk_i ;
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wire wb_clk = wb_clk_i ;
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