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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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`include "bus_commands.v"
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module PCI_PARITY_CHECK
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module PCI_PARITY_CHECK
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(
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(
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reset_in,
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reset_in,
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clk_in,
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clk_in,
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Line 79... |
pci_trdy_en_in,
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pci_trdy_en_in,
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pci_par_en_in,
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pci_par_en_in,
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pci_ad_out_in,
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pci_ad_out_in,
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pci_ad_reg_in,
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pci_ad_reg_in,
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pci_cbe_in_in,
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pci_cbe_in_in,
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pci_cbe_reg_in,
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pci_cbe_out_in,
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pci_cbe_out_in,
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pci_cbe_en_in,
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pci_cbe_en_in,
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pci_ad_en_in,
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pci_ad_en_in,
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par_err_response_in,
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par_err_response_in,
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par_err_detect_out,
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par_err_detect_out,
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| Line 111... |
Line 118... |
input pci_trdy_en_in ; // target ready output enable
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input pci_trdy_en_in ; // target ready output enable
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input pci_par_en_in ; // par enable input
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input pci_par_en_in ; // par enable input
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input [31:0] pci_ad_out_in ; // data driven by bridge to PCI
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input [31:0] pci_ad_out_in ; // data driven by bridge to PCI
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input [31:0] pci_ad_reg_in ; // data driven by other agents on PCI
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input [31:0] pci_ad_reg_in ; // data driven by other agents on PCI
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input [3:0] pci_cbe_in_in ; // cbe driven by outside agents
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input [3:0] pci_cbe_in_in ; // cbe driven by outside agents
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input [3:0] pci_cbe_reg_in ; // registered cbe driven by outside agents
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input [3:0] pci_cbe_out_in ; // cbe driven by pci master state machine
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input [3:0] pci_cbe_out_in ; // cbe driven by pci master state machine
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input pci_ad_en_in ; // ad enable input
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input pci_ad_en_in ; // ad enable input
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input par_err_response_in ; // parity error response bit from conf.space
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input par_err_response_in ; // parity error response bit from conf.space
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output par_err_detect_out ; // parity error detected signal out
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output par_err_detect_out ; // parity error detected signal out
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output perr_mas_detect_out ; // master asserted PERR or sampled PERR asserted
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output perr_mas_detect_out ; // master asserted PERR or sampled PERR asserted
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// FFs for frame input - used for determining whether PAR is sampled for address phase or for data phase
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// FFs for frame input - used for determining whether PAR is sampled for address phase or for data phase
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reg frame_dec2 ;
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reg frame_dec2 ;
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reg check_perr ;
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reg check_perr ;
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/*=======================================================================================================================
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/*=======================================================================================================================
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Input and output data sampling - used by parity checking and generation logic
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CBE lines' parity is needed for overall parity calculation
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=======================================================================================================================*/
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=======================================================================================================================*/
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wire par_cbe_out = pci_cbe_out_in[3] ^^ pci_cbe_out_in[2] ^^ pci_cbe_out_in[1] ^^ pci_cbe_out_in[0] ;
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wire par_cbe_out = pci_cbe_out_in[3] ^^ pci_cbe_out_in[2] ^^ pci_cbe_out_in[1] ^^ pci_cbe_out_in[0] ;
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wire par_cbe_include ;
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wire par_cbe_in = pci_cbe_reg_in[3] ^^ pci_cbe_reg_in[2] ^^ pci_cbe_reg_in[1] ^^ pci_cbe_reg_in[0] ;
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PAR_CBE_CRIT cbe_par_calc
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(
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.par_cbe_include_out(par_cbe_include),
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.par_cbe_out_in (par_cbe_out),
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.par_cbe_en_in (pci_cbe_en_in),
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.pci_cbe_in (pci_cbe_in_in)
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) ;
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reg cbe_par_reg ;
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always@( posedge reset_in or posedge clk_in )
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begin
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if (reset_in)
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cbe_par_reg <= #`FF_DELAY 1'b0 ;
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else
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cbe_par_reg <= #`FF_DELAY par_cbe_include ;
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end
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/*=======================================================================================================================
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/*=======================================================================================================================
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Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active
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Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active
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one clock cycle after data output enable. Depending on whether master is performing access or target is responding,
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one clock cycle after data output enable. Depending on whether master is performing access or target is responding,
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apropriate cbe data is included in parity generation.
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apropriate cbe data is included in parity generation. Non - registered CBE is used during reads through target SM
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=======================================================================================================================*/
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=======================================================================================================================*/
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// generate appropriate par signal
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// generate appropriate par signal
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wire data_par = (pci_ad_out_in[31] ^^ pci_ad_out_in[30] ^^ pci_ad_out_in[29] ^^ pci_ad_out_in[28]) ^^
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wire data_par = (pci_ad_out_in[31] ^^ pci_ad_out_in[30] ^^ pci_ad_out_in[29] ^^ pci_ad_out_in[28]) ^^
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(pci_ad_out_in[27] ^^ pci_ad_out_in[26] ^^ pci_ad_out_in[25] ^^ pci_ad_out_in[24]) ^^
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(pci_ad_out_in[27] ^^ pci_ad_out_in[26] ^^ pci_ad_out_in[25] ^^ pci_ad_out_in[24]) ^^
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Line 155... |
(pci_ad_out_in[11] ^^ pci_ad_out_in[10] ^^ pci_ad_out_in[9] ^^ pci_ad_out_in[8]) ^^
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(pci_ad_out_in[11] ^^ pci_ad_out_in[10] ^^ pci_ad_out_in[9] ^^ pci_ad_out_in[8]) ^^
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(pci_ad_out_in[7] ^^ pci_ad_out_in[6] ^^ pci_ad_out_in[5] ^^ pci_ad_out_in[4]) ^^
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(pci_ad_out_in[7] ^^ pci_ad_out_in[6] ^^ pci_ad_out_in[5] ^^ pci_ad_out_in[4]) ^^
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(pci_ad_out_in[3] ^^ pci_ad_out_in[2] ^^ pci_ad_out_in[1] ^^ pci_ad_out_in[0]) ;
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(pci_ad_out_in[3] ^^ pci_ad_out_in[2] ^^ pci_ad_out_in[1] ^^ pci_ad_out_in[0]) ;
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wire par_out_only = data_par ^^ par_cbe_out ;
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wire par_out_only = data_par ^^ par_cbe_out ;
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PAR_CRIT par_gen
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PAR_CRIT par_gen
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(
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(
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.par_out (pci_par_out),
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.par_out (pci_par_out),
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.par_out_in (par_out_only),
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.par_out_in (par_out_only),
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.pci_cbe_en_in (pci_cbe_en_in),
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.pci_cbe_en_in (pci_cbe_en_in),
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Line 200... |
assign pci_perr_out = perr_n ;
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assign pci_perr_out = perr_n ;
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// parity error output assignment
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// parity error output assignment
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//assign pci_perr_out = ~(perr && perr_generate) ;
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//assign pci_perr_out = ~(perr && perr_generate) ;
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wire non_critical_par = cbe_par_reg ^^ data_in_par ;
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wire non_critical_par = par_cbe_in ^^ data_in_par ;
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PERR_CRIT perr_crit_gen
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PERR_CRIT perr_crit_gen
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(
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(
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.perr_out (perr),
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.perr_out (perr),
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.perr_n_out (perr_n),
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.perr_n_out (perr_n),
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Line 231... |
always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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frame_dec2 <= #`FF_DELAY 1'b0 ;
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frame_dec2 <= #`FF_DELAY 1'b0 ;
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else
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else
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frame_dec2 <= #`FF_DELAY pci_frame_reg_in && ~pci_frame_en_in ;
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frame_dec2 <= #`FF_DELAY pci_frame_reg_in ;
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end
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end
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// address phase parity indicator
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// address phase parity error checking - done after address phase is detected - which is - when bridge's master is not driving frame,
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wire check_for_serr = ~pci_frame_reg_in && frame_dec2 ;
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// frame was asserted on previous cycle and was not asserted two cycles before.
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wire check_for_serr_on_first = ~pci_frame_reg_in && frame_dec2 && ~pci_frame_en_in ;
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reg check_for_serr_on_second ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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check_for_serr_on_second <= #`FF_DELAY 1'b0 ;
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else
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check_for_serr_on_second <= #`FF_DELAY check_for_serr_on_first && ( pci_cbe_reg_in == `BC_DUAL_ADDR_CYC ) ;
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end
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wire check_for_serr = check_for_serr_on_first || check_for_serr_on_second ;
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wire serr_generate = check_for_serr && serr_enable_in && par_err_response_in ;
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wire serr_generate = check_for_serr && serr_enable_in && par_err_response_in ;
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SERR_EN_CRIT serr_en_crit_gen
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SERR_EN_CRIT serr_en_crit_gen
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(
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(
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.serr_en_out (pci_serr_en_out),
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.serr_en_out (pci_serr_en_out),
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Line 298... |
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// assign output for parity error detected bit
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// assign output for parity error detected bit
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assign par_err_detect_out = ~pci_serr_out_in || ~pci_perr_out_in || perr_sampled ;
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assign par_err_detect_out = ~pci_serr_out_in || ~pci_perr_out_in || perr_sampled ;
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// FF indicating that that last operation was done as bus master
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// FF indicating that that last operation was done as bus master
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reg frame_and_irdy_en_prev ;
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reg frame_and_irdy_en_prev_prev ;
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reg master_perr_report ;
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reg master_perr_report ;
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always@(posedge reset_in or posedge clk_in)
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always@(posedge reset_in or posedge clk_in)
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begin
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begin
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if ( reset_in )
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if ( reset_in )
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begin
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master_perr_report <= #`FF_DELAY 1'b0 ;
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master_perr_report <= #`FF_DELAY 1'b0 ;
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frame_and_irdy_en_prev <= #`FF_DELAY 1'b0 ;
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frame_and_irdy_en_prev_prev <= #`FF_DELAY 1'b0 ;
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end
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else
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else
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master_perr_report <= #`FF_DELAY pci_irdy_en_in ;
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begin
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master_perr_report <= #`FF_DELAY frame_and_irdy_en_prev_prev ;
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frame_and_irdy_en_prev <= #`FF_DELAY pci_irdy_en_in && pci_frame_en_in ;
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frame_and_irdy_en_prev_prev <= #`FF_DELAY frame_and_irdy_en_prev ;
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end
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end
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end
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assign perr_mas_detect_out = master_perr_report && ( (par_err_response_in && perr_sampled) || pci_perr_en_reg ) ;
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assign perr_mas_detect_out = master_perr_report && ( (par_err_response_in && perr_sampled) || pci_perr_en_reg ) ;
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endmodule
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endmodule
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