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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/08/21 20:55:14 tadejm
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// Corrected bug when writing to FIFO (now it is registered).
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//
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// Revision 1.8 2003/08/08 16:36:33 tadejm
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// Revision 1.8 2003/08/08 16:36:33 tadejm
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
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//
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//
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// Revision 1.7 2003/01/27 16:49:31 mihad
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// Revision 1.7 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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frame_reg_in,
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frame_reg_in,
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fetch_pcir_fifo_in,
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fetch_pcir_fifo_in,
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load_medium_reg_in,
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load_medium_reg_in,
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sel_fifo_mreg_in,
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sel_fifo_mreg_in,
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sel_conf_fifo_in,
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sel_conf_fifo_in,
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fetch_conf_in,
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load_to_pciw_fifo_in,
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load_to_pciw_fifo_in,
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load_to_conf_in,
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load_to_conf_in,
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same_read_out,
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same_read_out,
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norm_access_to_config_out,
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norm_access_to_config_out,
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Line 154... |
pciw_fifo_full_in,
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pciw_fifo_full_in,
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wbw_fifo_empty_in,
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wbw_fifo_empty_in,
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wbu_del_read_comp_pending_in,
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wbu_del_read_comp_pending_in,
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// Configuration space signals
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// Configuration space signals
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conf_hit_out,
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conf_addr_out,
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conf_addr_out,
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conf_data_out,
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conf_data_out,
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conf_data_in,
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conf_data_in,
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conf_be_out,
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conf_be_out,
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conf_we_out,
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conf_we_out,
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input frame_reg_in ; // FRAME input signal - registered
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input frame_reg_in ; // FRAME input signal - registered
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input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
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input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
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input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
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input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
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input fetch_conf_in ; // Read enable for configuration space registers
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input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
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input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
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input load_to_conf_in ; // Write enable to Configuration space registers
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input load_to_conf_in ; // Write enable to Configuration space registers
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/*==================================================================================================================
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/*==================================================================================================================
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/*==================================================================================================================
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/*==================================================================================================================
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Configuration space signals - from and to registers
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Configuration space signals - from and to registers
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==================================================================================================================*/
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==================================================================================================================*/
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// BUS for reading and writing to configuration space registers
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// BUS for reading and writing to configuration space registers
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output conf_hit_out ; // like "chip select" for configuration space
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output [11:0] conf_addr_out ; // address to configuration space when there is access to it
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output [11:0] conf_addr_out ; // address to configuration space when there is access to it
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output [31:0] conf_data_out ; // data to configuration space - for writing to registers
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output [31:0] conf_data_out ; // data to configuration space - for writing to registers
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input [31:0] conf_data_in ; // data from configuration space - for reading from registers
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input [31:0] conf_data_in ; // data from configuration space - for reading from registers
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output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
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output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
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output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
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output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
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