URL
https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] [pci_user_constants.v] - Diff between revs 86 and 106
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 86 |
Rev 106 |
Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2003/03/14 15:31:57 mihad
|
|
// Entered the option to disable no response counter in wb master.
|
|
//
|
// Revision 1.7 2003/01/27 17:05:50 mihad
|
// Revision 1.7 2003/01/27 17:05:50 mihad
|
// Updated.
|
// Updated.
|
//
|
//
|
// Revision 1.6 2003/01/27 16:51:19 mihad
|
// Revision 1.6 2003/01/27 16:51:19 mihad
|
// Old files with wrong names removed.
|
// Old files with wrong names removed.
|
Line 232... |
Line 235... |
|
|
// define the macro below to disable internal retry generation in the wishbone master interface
|
// define the macro below to disable internal retry generation in the wishbone master interface
|
// used when wb master accesses extremly slow devices.
|
// used when wb master accesses extremly slow devices.
|
`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
|
`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
|
|
|
No newline at end of file
|
No newline at end of file
|
|
//`define PCI_WB_REV_B3
|
|
//`define PCI_WBS_B3_RTY_DISABLE
|
|
|
|
//`define PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.