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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] [pci_wbr_fifo_control.v] - Diff between revs 88 and 104
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| Rev 88 |
Rev 104 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.6 2002/11/27 20:36:12 mihad
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// Revision 1.6 2002/11/27 20:36:12 mihad
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// Changed the code a bit to make it more readable.
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// Changed the code a bit to make it more readable.
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Line 213... |
// grey coded address for status generation in write clock domain
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// grey coded address for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wgrey_addr <= #`FF_DELAY 0 ;
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wgrey_addr <= #1 0 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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begin
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begin
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wgrey_addr <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_addr <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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end
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end
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// write address counter - nothing special except initial value
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// write address counter - nothing special except initial value
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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