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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/08/12 13:58:19 mihad
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// Module that converts slave WISHBONE B3 accesses to
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// WISHBONE B2 accesses with CAB.
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//
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//
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//
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module pci_wbs_wbb3_2_wbb2
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module pci_wbs_wbb3_2_wbb2
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(
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(
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wb_clk_i,
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wb_clk_i,
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// 1st condition - pci bridge is signaling an error
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// 1st condition - pci bridge is signaling an error
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end_cycle[0] = wbs_err_i ;
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end_cycle[0] = wbs_err_i ;
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// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
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// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
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end_cycle[1] = wbs_rty_i `ifdef PCI_WBS_B3_RTY_DISABLE & 1'b0 `endif ;
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end_cycle[1] = wbs_rty_i
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`ifdef PCI_WBS_B3_RTY_DISABLE
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& 1'b0
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`endif
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;
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// 3rd condition - end non burst cycles as soon as pci bridge response is received
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// 3rd condition - end non burst cycles as soon as pci bridge response is received
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end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
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end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
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// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
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// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
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end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
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end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
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if (wbs_dat_i_o_valid)
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if (wbs_dat_i_o_valid)
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begin
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begin
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if (wbs_ack_i | wbs_err_i `ifdef PCI_WBS_B3_RTY_DISABLE `else | wbs_rty_i `endif)
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if (wbs_ack_i | wbs_err_i
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`ifdef PCI_WBS_B3_RTY_DISABLE
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`else
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| wbs_rty_i
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`endif
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)
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wbs_dat_i_o_valid <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)
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if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)
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assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
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assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
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(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) |
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(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) |
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(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
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(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
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endmodule
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endmodule
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