| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Repaired initial sync value in fifos.
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.7 2002/11/27 20:36:10 mihad
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// Revision 1.7 2002/11/27 20:36:10 mihad
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// Changed the code a bit to make it more readable.
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// Changed the code a bit to make it more readable.
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| Line 217... |
Line 222... |
// grey coded address pipeline for status generation in read clock domain
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// grey coded address pipeline for status generation in read clock domain
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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rgrey_addr <= #`FF_DELAY 0 ;
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rgrey_addr <= #1 0 ;
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rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
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rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
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end
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end
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else if (flush_in)
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else if (flush_in)
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begin
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begin
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// when fifo is flushed, load the register values from the write clock domain.
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// when fifo is flushed, load the register values from the write clock domain.
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// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
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// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
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rgrey_addr <= #`FF_DELAY wgrey_addr ;
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rgrey_addr <= #1 wgrey_addr ;
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rgrey_next <= #`FF_DELAY wgrey_next ;
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rgrey_next <= #`FF_DELAY wgrey_next ;
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end
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end
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else if (rallow)
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else if (rallow)
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begin
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begin
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// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
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// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #1 rgrey_next ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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| Line 245... |
Line 250... |
// grey coded address pipeline for status generation in write clock domain
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// grey coded address pipeline for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wgrey_addr <= #`FF_DELAY 0 ;
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wgrey_addr <= #1 0 ;
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wgrey_next <= #`FF_DELAY 1 ;
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wgrey_next <= #`FF_DELAY 1 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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begin
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begin
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_addr <= #1 wgrey_next ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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end
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end
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// write address binary counter - nothing special except initial value
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// write address binary counter - nothing special except initial value
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