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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/08/03 18:05:06 mihad
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// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
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// Doesn't support full speed bursts yet.
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//
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// Revision 1.8 2003/03/14 15:31:57 mihad
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// Revision 1.8 2003/03/14 15:31:57 mihad
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// Entered the option to disable no response counter in wb master.
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// Entered the option to disable no response counter in wb master.
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//
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//
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// Revision 1.7 2003/01/27 17:05:50 mihad
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// Revision 1.7 2003/01/27 17:05:50 mihad
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// Updated.
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// Updated.
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// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
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// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
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// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
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// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// WB_FIFO_RAM_ADDR_LENGTH.
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// WB_FIFO_RAM_ADDR_LENGTH.
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`define WBW_ADDR_LENGTH 3
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`define WBW_ADDR_LENGTH 7
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`define WBR_ADDR_LENGTH 5
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`define WBR_ADDR_LENGTH 7
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`define PCIW_ADDR_LENGTH 3
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`define PCIW_ADDR_LENGTH 7
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`define PCIR_ADDR_LENGTH 3
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`define PCIR_ADDR_LENGTH 7
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`define FPGA
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//`define FPGA
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`define XILINX
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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//`define WB_RAM_DONT_SHARE
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`define PCI_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef FPGA
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`ifdef XILINX
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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//`define PCI_XILINX_RAMB4
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`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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`define PCI_XILINX_DIST_RAM
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`endif
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`else
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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// `define WB_ARTISAN_SDP
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// `define WB_ARTISAN_SDP
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// `define PCI_ARTISAN_SDP
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// `define PCI_ARTISAN_SDP
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// `define PCI_VS_STP
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// `define PCI_VS_STP
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// `define WB_VS_STP
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// `define WB_VS_STP
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`endif
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`endif
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// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
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// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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// smaller the number here, faster the decoder operation
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`define PCI_NUM_OF_DEC_ADDR_LINES 12
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`define PCI_NUM_OF_DEC_ADDR_LINES 20
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// no. of PCI Target IMAGES
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// no. of PCI Target IMAGES
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// - PCI provides 6 base address registers for image implementation.
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// - PCI provides 6 base address registers for image implementation.
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// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
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// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
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// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
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// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
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// is no access to Configuration space possible from PCI bus.
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// is no access to Configuration space possible from PCI bus.
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// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
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// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
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// or GUEST implementation.
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// or GUEST implementation.
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`ifdef HOST
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`define PCI_IMAGE0
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//`define PCI_IMAGE0
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`endif
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`endif
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`endif
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`endif
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//`define PCI_IMAGE2
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`define PCI_IMAGE2
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//`define PCI_IMAGE3
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`define PCI_IMAGE3
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//`define PCI_IMAGE4
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`define PCI_IMAGE4
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//`define PCI_IMAGE5
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`define PCI_IMAGE5
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// initial value for PCI image address masks. Address masks can be defined in enabled state,
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// initial value for PCI image address masks. Address masks can be defined in enabled state,
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// to allow device independent software to detect size of image and map base addresses to
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// to allow device independent software to detect size of image and map base addresses to
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// memory space. If initial mask for an image is defined as 0, then device independent software
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// memory space. If initial mask for an image is defined as 0, then device independent software
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// won't detect base address implemented and device dependent software will have to configure
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// won't detect base address implemented and device dependent software will have to configure
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// number defined here specifies how many MS bits in WB address are compared with base address, to decode
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// number defined here specifies how many MS bits in WB address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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// smaller the number here, faster the decoder operation
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`define WB_NUM_OF_DEC_ADDR_LINES 3
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`define WB_NUM_OF_DEC_ADDR_LINES 20
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// no. of WISHBONE Slave IMAGES
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// no. of WISHBONE Slave IMAGES
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// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
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// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
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// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
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// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
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// WB Image 1 is always implemented and user doesnt need to specify its definition
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// WB Image 1 is always implemented and user doesnt need to specify its definition
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// WB images' 2 through 5 implementation by defining each one.
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// WB images' 2 through 5 implementation by defining each one.
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//`define WB_IMAGE2
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`define WB_IMAGE2
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//`define WB_IMAGE3
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`define WB_IMAGE3
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//`define WB_IMAGE4
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`define WB_IMAGE4
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//`define WB_IMAGE5
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`define WB_IMAGE5
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// If this define is commented out, then address translation will not be implemented.
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// If this define is commented out, then address translation will not be implemented.
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// addresses will pass through bridge unchanged, regardles of address translation enable bits.
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// addresses will pass through bridge unchanged, regardles of address translation enable bits.
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// Address translation also slows down the decoding
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// Address translation also slows down the decoding
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//`define ADDR_TRAN_IMPL
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`define ADDR_TRAN_IMPL
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// slower decode speed can be used, to provide enough time for address to be decoded.
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// slower decode speed can be used, to provide enough time for address to be decoded.
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`define WB_DECODE_FAST
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`define WB_DECODE_FAST
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//`define WB_DECODE_MEDIUM
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//`define WB_DECODE_MEDIUM
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//`define WB_DECODE_SLOW
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//`define WB_DECODE_SLOW
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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`define WB_CONFIGURATION_BASE 20'hF300_0
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`define WB_CONFIGURATION_BASE 20'h0000_0
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// Turn registered WISHBONE slave outputs on or off
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// Turn registered WISHBONE slave outputs on or off
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// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
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// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
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// outputs to internals of the core.
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// outputs to internals of the core.
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//`define REGISTER_WBS_OUTPUTS
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//`define REGISTER_WBS_OUTPUTS
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Line 229... |
`define HEADER_REVISION_ID 8'h01
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`define HEADER_REVISION_ID 8'h01
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// Turn registered WISHBONE master outputs on or off
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// Turn registered WISHBONE master outputs on or off
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// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
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// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
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// outputs to internals of the core.
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// outputs to internals of the core.
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`define REGISTER_WBM_OUTPUTS
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//`define REGISTER_WBM_OUTPUTS
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// MAX Retry counter value for WISHBONE Master state-machine
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// MAX Retry counter value for WISHBONE Master state-machine
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// This value is 8-bit because of 8-bit retry counter !!!
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// This value is 8-bit because of 8-bit retry counter !!!
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`define WB_RTY_CNT_MAX 8'hff
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`define WB_RTY_CNT_MAX 8'hff
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// define the macro below to disable internal retry generation in the wishbone master interface
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// define the macro below to disable internal retry generation in the wishbone master interface
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// used when wb master accesses extremly slow devices.
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// used when wb master accesses extremly slow devices.
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`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
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//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
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//`define PCI_WB_REV_B3
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`define PCI_WB_REV_B3
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//`define PCI_WBS_B3_RTY_DISABLE
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//`define PCI_WBS_B3_RTY_DISABLE
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//`define PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS
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No newline at end of file
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No newline at end of file
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`ifdef GUEST
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`define PCI_CPCI_HS_IMPLEMENT
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`endif
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No newline at end of file
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