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[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] [pci_wbs_wbb3_2_wbb2.v] - Diff between revs 126 and 132
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| Rev 126 |
Rev 132 |
| Line 38... |
Line 38... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/12/01 16:20:56 simons
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// ifdef - endif statements put in separate lines for flint compatibility.
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//
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// Revision 1.1 2003/08/12 13:58:19 mihad
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// Revision 1.1 2003/08/12 13:58:19 mihad
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// Module that converts slave WISHBONE B3 accesses to
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// Module that converts slave WISHBONE B3 accesses to
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// WISHBONE B2 accesses with CAB.
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// WISHBONE B2 accesses with CAB.
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//
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//
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//
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//
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| Line 124... |
Line 127... |
wbs_dat_i_o <= 32'h0 ;
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wbs_dat_i_o <= 32'h0 ;
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wbs_dat_o_o <= 32'h0 ;
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wbs_dat_o_o <= 32'h0 ;
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wbs_sel_o <= 4'h0 ;
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wbs_sel_o <= 4'h0 ;
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wbs_we_o <= 1'b0 ;
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wbs_we_o <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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else
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else
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begin:transfer_and_transfer_adr_ctrl_blk
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begin:transfer_and_transfer_adr_ctrl_blk
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reg start_cycle ;
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reg start_cycle ;
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reg [3:0] end_cycle ;
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reg [3:0] end_cycle ;
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| Line 184... |
Line 188... |
case (wbs_bte_i)
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case (wbs_bte_i)
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2'b00: begin
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2'b00: begin
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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end
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end
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2'b01: begin
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2'b01: begin
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if (wbs_adr_i[3:0] == 4'b0000)
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if (wbs_adr_i[3:2] == 2'b00)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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2'b10: begin
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2'b10: begin
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if (wbs_adr_i[4:0] == 5'b00000)
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if (wbs_adr_i[4:2] == 3'b000)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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2'b11: begin
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2'b11: begin
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if (wbs_adr_i[5:0] == 6'b000000)
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if (wbs_adr_i[5:2] == 4'b0000)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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endcase
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endcase
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