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[/] [pci/] [tags/] [rel_00/] [rtl/] [verilog/] [delayed_sync.v] - Diff between revs 21 and 33
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| Rev 21 |
Rev 33 |
| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
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req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
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end
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end
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synchronizer_flop rty_exp_back_prop_sync
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synchronizer_flop rty_exp_back_prop_sync
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(
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(
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.data_in (req_rty_exp_reg),
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.data_in (req_rty_exp_reg && req_rty_exp_clr),
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.clk_out (comp_clk_in),
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.clk_out (comp_clk_in),
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.sync_data_out (sync_comp_rty_exp_clr),
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.sync_data_out (sync_comp_rty_exp_clr),
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.async_reset (reset_in)
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.async_reset (reset_in)
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) ;
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) ;
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