URL
https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [rel_00/] [rtl/] [verilog/] [mas_ch_state_crit.v] - Diff between revs 6 and 21
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 6 |
Rev 21 |
Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/10/05 08:14:28 mihad
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
|
//
|
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
|
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
|
// New project directory structure
|
// New project directory structure
|
//
|
//
|
//
|
//
|
|
|
// module is used to separate logic which uses criticaly constrained inputs from slower logic.
|
// module is used to separate logic which uses criticaly constrained inputs from slower logic.
|
// It is used to synthesize critical timing logic separately with faster cells or without optimization
|
// It is used to synthesize critical timing logic separately with faster cells or without optimization
|
|
|
// Module is used in master state machine for state machine clock enable driving
|
// Module is used in master state machine for state machine clock enable driving
|
|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
|
|
module MAS_CH_STATE_CRIT
|
module MAS_CH_STATE_CRIT
|
(
|
(
|
change_state_out,
|
change_state_out,
|
ch_state_med_in,
|
ch_state_med_in,
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.