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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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//
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`include "constants.v"
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`include "constants.v"
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`include "timescale.v"
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// module inferes a single IOB output block as known in FPGA architectures
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// module inferes a single IOB output block as known in FPGA architectures
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// It provides data flip flop with clock enable and output enable flip flop with clock enable
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// It provides data flip flop with clock enable and output enable flip flop with clock enable
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// This is tested in Xilinx FPGA - active low output enable
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// This is tested in Xilinx FPGA - active low output enable
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// Check polarity of output enable flip flop for specific architecure.
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// Check polarity of output enable flip flop for specific architecure.
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