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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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// Module is used for registering PCI input signals
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// Module is used for registering PCI input signals
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// It provides data flip flops with reset
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// It provides data flip flops with reset
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module PCI_IN_REG
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module PCI_IN_REG
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(
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(
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reset_in,
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reset_in,
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pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
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pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
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pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
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pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
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pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
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pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
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pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
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pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
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end
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end
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else
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else
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begin
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begin
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pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
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pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
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pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
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pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
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pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
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pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
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pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
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pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
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pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;
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pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;
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pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;
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pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;
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pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;
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pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;
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end
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end
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
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else
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pci_ad_reg_out <= #`FF_DELAY pci_ad_in ;
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pci_ad_reg_out <= #`FF_DELAY pci_ad_in ;
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end
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
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else
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pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
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pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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