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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// module includes pci master state machine and surrounding logic
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// module includes pci master state machine and surrounding logic
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`include "bus_commands.v"
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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module PCI_MASTER32_SM
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module PCI_MASTER32_SM
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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Line 101... |
rdy_in,
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rdy_in,
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last_in,
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last_in,
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next_data_in,
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next_data_in,
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next_be_in,
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next_be_in,
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next_last_in,
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next_last_in,
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load_next_out,
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ad_load_out,
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ad_load_on_transfer_out,
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wait_out,
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wait_out,
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wtransfer_out,
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wtransfer_out,
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rtransfer_out,
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rtransfer_out,
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retry_out,
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retry_out,
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werror_out,
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rerror_out,
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rerror_out,
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first_out,
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first_out,
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mabort_out,
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mabort_out,
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latency_tim_val_in
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latency_tim_val_in
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) ;
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) ;
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Line 184... |
// status outputs
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// status outputs
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output wait_out, // wait indicates to the backend that dataphases are not in progress on PCI bus
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output wait_out, // wait indicates to the backend that dataphases are not in progress on PCI bus
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wtransfer_out, // on any rising clock edge that this status is 1, data is transferred - heavy constraints here
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wtransfer_out, // on any rising clock edge that this status is 1, data is transferred - heavy constraints here
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rtransfer_out, // registered transfer indicator - when 1 indicates that data was transfered on previous clock cycle
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rtransfer_out, // registered transfer indicator - when 1 indicates that data was transfered on previous clock cycle
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retry_out, // retry status output - when target signals a retry
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retry_out, // retry status output - when target signals a retry
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werror_out, // error output - when 1 indicates that error (target abort) occured on current dataphase - heavy constraints
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rerror_out, // registered error output - when 1 indicates that error was signalled by a target on previous clock cycle
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rerror_out, // registered error output - when 1 indicates that error was signalled by a target on previous clock cycle
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first_out , // indicates whether or not any data was transfered in current transaction
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first_out , // indicates whether or not any data was transfered in current transaction
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mabort_out; // master abort indicator
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mabort_out; // master abort indicator
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reg wait_out ;
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reg wait_out ;
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input [31:0] next_data_in ;
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input [31:0] next_data_in ;
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input [3:0] next_be_in ;
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input [3:0] next_be_in ;
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input next_last_in ;
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input next_last_in ;
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// clock enable for data output flip-flops - whenever data is transfered, sm loads next data to those flip flops
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// clock enable for data output flip-flops - whenever data is transfered, sm loads next data to those flip flops
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output load_next_out ;
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output ad_load_out,
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ad_load_on_transfer_out ;
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// parameters - states - one hot
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// parameters - states - one hot
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// idle state
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// idle state
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parameter S_IDLE = 4'h1 ;
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parameter S_IDLE = 4'h1 ;
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Line 278... |
wire do_write = bc_in[0] ;
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wire do_write = bc_in[0] ;
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// latency timer
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// latency timer
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reg [7:0] latency_timer ;
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reg [7:0] latency_timer ;
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wire latency_time_out = ~(
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wire latency_timer_enable = sm_data_phases ;
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wire latency_timer_load = ~sm_address && ~sm_data_phases ;
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wire latency_timer_exp = ~(
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(latency_timer[7] || latency_timer[6] || latency_timer[5] || latency_timer[4]) ||
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(latency_timer[7] || latency_timer[6] || latency_timer[5] || latency_timer[4]) ||
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(latency_timer[3] || latency_timer[2] || latency_timer_load)
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(latency_timer[3] || latency_timer[2] || latency_timer[1] )
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) ;
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) ;
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// flip flop for registering latency timer timeout
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wire latency_timer_enable = (sm_address || sm_data_phases) && ~latency_time_out ;
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reg latency_time_out ;
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wire latency_timer_load = ~sm_address && ~sm_data_phases ;
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always@(posedge clk_in or posedge reset_in)
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begin
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if (reset_in)
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latency_time_out <= #`FF_DELAY 1'b0 ;
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else
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latency_time_out <= #`FF_DELAY latency_timer_exp ;
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end
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always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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latency_timer <= #`FF_DELAY 8'hFF ;
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latency_timer <= #`FF_DELAY 8'h00 ;
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else
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else
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if ( latency_timer_load )
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if ( latency_timer_load )
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latency_timer <= #`FF_DELAY latency_tim_val_in ;
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latency_timer <= #`FF_DELAY latency_tim_val_in ;
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else
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else
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if ( latency_timer_enable && ~latency_time_out) // latency timer counts down until it expires - then it stops
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if ( latency_timer_enable) // latency timer counts down until it expires - then it stops
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latency_timer <= #`FF_DELAY latency_timer - 1'b1 ;
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latency_timer <= #`FF_DELAY latency_timer - 1'b1 ;
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end
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end
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// master abort indicators - when decode time out occurres and still no target response is received
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// master abort indicators - when decode time out occurres and still no target response is received
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wire do_master_abort = decode_to && pci_trdy_in && pci_stop_in && pci_devsel_in ;
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wire do_master_abort = decode_to && pci_trdy_in && pci_stop_in && pci_devsel_in ;
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Line 337... |
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// frame control logic
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// frame control logic
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// frame is forced to 0 (active) when state machine is in idle state, since only possible next state is address state which always drives frame active
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// frame is forced to 0 (active) when state machine is in idle state, since only possible next state is address state which always drives frame active
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wire force_frame = ~sm_idle ;
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wire force_frame = ~sm_idle ;
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// slow signal for frame calculated from various registers in the core
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// slow signal for frame calculated from various registers in the core
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wire slow_frame = last_in || timeout || (next_last_in && sm_data_phases) || mabort1 ;
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wire slow_frame = last_in || (latency_time_out && pci_gnt_in) || (next_last_in && sm_data_phases) || mabort1 ;
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// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted
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// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted
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// (STOP)
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// (STOP)
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FRAME_CRIT frame_iob_feed
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FRAME_CRIT frame_iob_feed
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(
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(
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.pci_frame_out (pci_frame_out),
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.pci_frame_out (pci_frame_out),
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Line 398... |
assign wtransfer_out = ~pci_trdy_in ;
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assign wtransfer_out = ~pci_trdy_in ;
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// registered transfer status output - calculated from registered target response inputs
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// registered transfer status output - calculated from registered target response inputs
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assign rtransfer_out = ~(pci_trdy_reg_in || pci_devsel_reg_in) ;
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assign rtransfer_out = ~(pci_trdy_reg_in || pci_devsel_reg_in) ;
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// current error status - calculated directly from target signals and therefore critical
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assign werror_out = (~pci_stop_in && pci_devsel_in) ;
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// registered error status - calculated from registered target response inputs
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// registered error status - calculated from registered target response inputs
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assign rerror_out = (~pci_stop_reg_in && pci_devsel_reg_in) ;
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assign rerror_out = (~pci_stop_reg_in && pci_devsel_reg_in) ;
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// retry is signalled to backend depending on registered target response or when latency timer expires
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// retry is signalled to backend depending on registered target response or when latency timer expires
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assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
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assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ;
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// AD output flip flops' clock enable
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// AD output flip flops' clock enable
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// when address phase is about to be finished
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// when address phase is about to be finished
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wire load_force = (sm_idle && u_have_pci_bus) || sm_address ;
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wire ad_load_slow = sm_address ;
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wire ad_load_on_grant = sm_idle && pci_frame_in && pci_irdy_in ;
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// next data loading is allowed when state machine is in transfer state and operation is a write
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MAS_AD_LOAD_CRIT mas_ad_load_feed
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wire load_allow = sm_data_phases && do_write ;
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// actual loading during data phases is done by monitoring critical target response signals - separate module
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MAS_LOAD_NEXT_CRIT ad_iob_ce
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(
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(
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.load_next_out (load_next_out),
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.ad_load_out (ad_load_out),
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.load_force_in (load_force),
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.ad_load_in (ad_load_slow),
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.load_allow_in (load_allow),
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.ad_load_on_grant_in (ad_load_on_grant),
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.pci_trdy_in (pci_trdy_in)
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.pci_gnt_in (pci_gnt_in)
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) ;
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) ;
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// next data loading is allowed when state machine is in transfer state and operation is a write
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assign ad_load_on_transfer_out = sm_data_phases && do_write ;
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// request for a bus is issued anytime when backend is requesting a transaction and state machine is in idle state
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// request for a bus is issued anytime when backend is requesting a transaction and state machine is in idle state
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assign pci_req_out = ~(req_in && sm_idle) ;
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assign pci_req_out = ~(req_in && sm_idle) ;
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// change state signal is actually clock enable for state register
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// change state signal is actually clock enable for state register
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// Non critical path for state change enable:
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// Non critical path for state change enable:
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Line 448... |
.pci_stop_in (pci_stop_in)
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.pci_stop_in (pci_stop_in)
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) ;
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) ;
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// ad enable driving
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// ad enable driving
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// also divided in several categories - from less critical to most critical in separate module
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// also divided in several categories - from less critical to most critical in separate module
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wire ad_en_slowest = do_write && (sm_address || sm_data_phases && ~pci_frame_out_in) ;
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//wire ad_en_slowest = do_write && (sm_address || sm_data_phases && ~pci_frame_out_in) ;
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wire ad_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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//wire ad_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire ad_en_slow = ad_en_on_grant && ~pci_gnt_in || ad_en_slowest ;
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//wire ad_en_slow = ad_en_on_grant && ~pci_gnt_in || ad_en_slowest ;
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wire ad_en_keep = sm_data_phases && do_write && (pci_frame_out_in && ~mabort1 && ~mabort2) ;
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//wire ad_en_keep = sm_data_phases && do_write && (pci_frame_out_in && ~mabort1 && ~mabort2) ;
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wire ad_en_slow = do_write && ( sm_address || ( sm_data_phases && !( ( pci_frame_out_in && mabort1 ) || mabort2 ) ) ) ;
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wire ad_en_on_grant = ( sm_idle && pci_frame_in && pci_irdy_in ) || sm_turn_arround ;
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// critical timing ad enable - calculated from target response inputs
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// critical timing ad enable - calculated from grant input
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MAS_AD_EN_CRIT ad_iob_oe_feed
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MAS_AD_EN_CRIT ad_iob_oe_feed
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(
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(
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.pci_ad_en_out (pci_ad_en_out),
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.pci_ad_en_out (pci_ad_en_out),
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.ad_en_slow_in (ad_en_slow),
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.ad_en_slow_in (ad_en_slow),
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.ad_en_keep_in (ad_en_keep),
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.ad_en_on_grant_in (ad_en_on_grant),
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.pci_stop_in (pci_stop_in),
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.pci_gnt_in (pci_gnt_in)
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.pci_trdy_in (pci_trdy_in)
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) ;
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) ;
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// cbe enable driving
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// cbe enable driving
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wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ;
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wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ;
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Line 521... |
// indicate the state
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// indicate the state
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sm_idle = 1'b1 ;
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sm_idle = 1'b1 ;
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// assign next state - only possible is address - if state machine is supposed to stay in idle state
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// assign next state - only possible is address - if state machine is supposed to stay in idle state
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// outside signals disable the clock
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// outside signals disable the clock
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next_state = S_ADDRESS ;
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next_state = S_ADDRESS ;
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wdata_selector = SEL_DATA_BE ;
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end
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end
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S_ADDRESS: begin
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S_ADDRESS: begin
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// indicate the state
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// indicate the state
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sm_address = 1'b1 ;
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sm_address = 1'b1 ;
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// select appropriate data/be for outputs
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// select appropriate data/be for outputs
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wdata_selector = SEL_DATA_BE ;
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wdata_selector = SEL_NEXT_DATA_BE ;
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// only possible next state is transfer state
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// only possible next state is transfer state
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next_state = S_TRANSFER ;
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next_state = S_TRANSFER ;
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end
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end
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S_TRANSFER: begin
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S_TRANSFER: begin
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Line 563... |
default: next_state = S_IDLE ;
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default: next_state = S_IDLE ;
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endcase
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endcase
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end
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end
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// ad and cbe lines multiplexer for write data
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// ad and cbe lines multiplexer for write data
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always@(wdata_selector or address_in or bc_in or data_in or be_in or next_data_in or next_be_in)
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reg [1:0] rdata_selector ;
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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case ( wdata_selector )
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if ( reset_in )
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rdata_selector <= #`FF_DELAY SEL_ADDR_BC ;
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else
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if ( change_state )
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rdata_selector <= #`FF_DELAY wdata_selector ;
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end
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always@(rdata_selector or address_in or bc_in or data_in or be_in or next_data_in or next_be_in)
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begin
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case ( rdata_selector )
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SEL_ADDR_BC: begin
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SEL_ADDR_BC: begin
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pci_ad_out = address_in ;
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pci_ad_out = address_in ;
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pci_cbe_out = bc_in ;
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pci_cbe_out = bc_in ;
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end
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end
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| Line 597... |
Line 602... |
data_out = 32'hFFFF_FFFF ;
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data_out = 32'hFFFF_FFFF ;
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else
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else
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data_out = pci_ad_reg_in ;
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data_out = pci_ad_reg_in ;
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end
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end
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endmodule
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endmodule
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