| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/02/19 16:32:37 mihad
|
|
// Modified testbench and fixed some bugs
|
|
//
|
// Revision 1.3 2002/02/01 15:25:13 mihad
|
// Revision 1.3 2002/02/01 15:25:13 mihad
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
//
|
//
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
// Revision 1.2 2001/10/05 08:14:30 mihad
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
// Updated all files with inclusion of timescale file for simulation purposes.
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| Line 363... |
Line 366... |
wb_no_response_cnt <= #`FF_DELAY 4'h0 ;
|
wb_no_response_cnt <= #`FF_DELAY 4'h0 ;
|
else
|
else
|
wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
|
wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
|
end
|
end
|
// internal WB no response retry generator logic
|
// internal WB no response retry generator logic
|
always@(wait_for_wb_response or wb_no_response_cnt or ACK_I or ERR_I or RTY_I)
|
always@(wait_for_wb_response or wb_no_response_cnt)
|
begin
|
begin
|
if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
|
if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
|
begin
|
begin
|
wb_response_value <= 4'h0 ;
|
wb_response_value <= 4'h0 ;
|
set_retry <= 1'b1 ;
|
set_retry <= 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (ACK_I || ERR_I || RTY_I) // if device responded, then ZERO must be written into counter
|
|
wb_response_value <= 4'h0 ;
|
|
else
|
|
if (wait_for_wb_response)
|
if (wait_for_wb_response)
|
wb_response_value <= wb_no_response_cnt + 1'h1 ; // count clocks when no response
|
wb_response_value <= wb_no_response_cnt + 1'h1 ; // count clocks when no response
|
else
|
else
|
wb_response_value <= wb_no_response_cnt ;
|
wb_response_value <= 4'h0 ;
|
set_retry <= 1'b0 ;
|
set_retry <= 1'b0 ;
|
end
|
end
|
end
|
end
|
|
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter ; // output from retry counter
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
|
reg rty_counter_max_value ; // signal tells when retry counter riches maximum value!
|
reg rty_counter_almost_max_value ; // signal tells when retry counter riches maximum value - 1!
|
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
|
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
|
|
|
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
|
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
|
// for reseting the retry counter
|
// for reseting the retry counter
|
always@(posedge reset_in or posedge wb_clock_in)
|
always@(posedge reset_in or posedge wb_clock_in)
|
| Line 415... |
Line 415... |
end
|
end
|
end
|
end
|
// Retry counter logic
|
// Retry counter logic
|
always@(rty_counter)
|
always@(rty_counter)
|
begin
|
begin
|
if(rty_counter == `WB_RTY_CNT_MAX) // stop counting
|
if(rty_counter == `WB_RTY_CNT_MAX - 1'b1) // stop counting
|
begin
|
begin
|
rty_counter_in <= rty_counter ;
|
rty_counter_in <= rty_counter ;
|
rty_counter_max_value <= 1'b1 ;
|
rty_counter_almost_max_value <= 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rty_counter_in <= rty_counter + 1'b1 ; // count up
|
rty_counter_in <= rty_counter + 1'b1 ; // count up
|
rty_counter_max_value <= 1'b0 ;
|
rty_counter_almost_max_value <= 1'b0 ;
|
end
|
end
|
end
|
end
|
|
|
/*reg [7:0] cache_line ; // output from cache line down-counter
|
|
reg [7:0] cache_line_in ; // input to cache line counter
|
|
reg cache_line_into_cnt ; // control signal for loading cache line size to counter
|
|
reg cache_line_count ; // control signal for count enable
|
|
reg cache_line_reg_used ; // if pci_cache_line_size is ZERO then all PCIR_FIFO is read
|
|
|
|
assign cache_line_wire = cache_line ;
|
|
// cache line size down-counter register control
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
|
begin
|
|
if (reset_in) // reset counter
|
|
cache_line <= #`FF_DELAY 8'h00 ;
|
|
else
|
|
cache_line <= #`FF_DELAY cache_line_in ; // count down or hold value depending on cache line counter logic
|
|
end
|
|
// cache line size down-counter logic
|
|
always@(cache_line_into_cnt or cache_line_count or pci_cache_line_size or cache_lsize_not_zero or cache_line)
|
|
begin
|
|
if (cache_line_into_cnt) // load cache line size into counter
|
|
begin
|
|
if (cache_lsize_not_zero)
|
|
cache_line_in = pci_cache_line_size ;
|
|
else
|
|
cache_line_in = 8'h01 ;
|
|
end
|
|
else
|
|
if (cache_line_count)
|
|
begin
|
|
cache_line_in = cache_line - 1'h1 ; // count down
|
|
end
|
|
else
|
|
begin
|
|
cache_line_in = cache_line ;
|
|
end
|
|
end
|
|
*/
|
|
|
|
|
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
|
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
|
reg [31:0] addr_cnt_in ; // input address value to address counter
|
reg [31:0] addr_cnt_in ; // input address value to address counter
|
reg addr_into_cnt ; // control signal for loading starting address into counter
|
reg addr_into_cnt ; // control signal for loading starting address into counter
|
reg addr_count ; // control signal for count enable
|
reg addr_count ; // control signal for count enable
|
reg [3:0] bc_register ; // used when error occures during writes!
|
reg [3:0] bc_register ; // used when error occures during writes!
|
| Line 611... |
Line 573... |
w_attempt or
|
w_attempt or
|
r_attempt or
|
r_attempt or
|
retried or
|
retried or
|
rty_i_delayed or
|
rty_i_delayed or
|
pci_tar_read_request or
|
pci_tar_read_request or
|
rty_counter_max_value or
|
rty_counter_almost_max_value or
|
|
set_retry or
|
last_data_to_pcir_fifo or
|
last_data_to_pcir_fifo or
|
first_wb_data_access or
|
first_wb_data_access or
|
last_data_from_pciw_fifo_reg
|
last_data_from_pciw_fifo_reg
|
)
|
)
|
begin
|
begin
|
| Line 631... |
Line 594... |
error_source_out <= 1'b0 ;
|
error_source_out <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
case ({w_attempt, r_attempt, retried})
|
case ({w_attempt, r_attempt, retried})
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
pciw_fifo_renable <= 1'b0 ; // the same data
|
pciw_fifo_renable <= 1'b0 ; // the same data
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt <= 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
if (rty_counter_max_value) // If retry counter reached maximum value
|
|
begin
|
|
n_state <= S_WRITE_ERR_RTY ;
|
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
|
error_source_out <= rty_i_delayed;
|
|
pci_error_sig_out <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
n_state <= S_WRITE ;
|
n_state <= S_WRITE ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
end
|
end
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
|
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
|
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
|
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
read_count_load <= 1'b0 ; // no need for cache line when there is write
|
n_state <= S_WRITE ;
|
n_state <= S_WRITE ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
end
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there was retry, the same transaction must be initiated
|
begin // If there was retry, the same transaction must be initiated
|
addr_into_cnt <= 1'b0 ; // the same address
|
addr_into_cnt <= 1'b0 ; // the same address
|
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
|
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
if (rty_counter_max_value) // If retry counter reached maximum value
|
|
begin
|
|
n_state <= S_READ_RTY;
|
|
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
|
|
end
|
|
else
|
|
begin
|
|
n_state <= S_READ ;
|
n_state <= S_READ ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
end
|
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
end
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
|
begin // If there is new transaction
|
begin // If there is new transaction
|
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
|
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
|
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
|
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
|
n_state <= S_READ ;
|
n_state <= S_READ ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
end
|
default : // stay in IDLE state
|
default : // stay in IDLE state
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
pciw_fifo_renable <= 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
read_count_load <= 1'b0 ;
|
read_count_load <= 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
write_rty_cnt_exp_out <= 1'b0 ;
|
|
read_rty_cnt_exp_out <= 1'b0 ;
|
|
error_source_out <= 1'b0 ;
|
|
pci_error_sig_out <= 1'b0 ;
|
|
end
|
end
|
endcase
|
endcase
|
wb_stb_o <= 1'b0 ;
|
wb_stb_o <= 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_we_o <= 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
wb_cyc_o <= 1'b0 ;
|
| Line 758... |
Line 687... |
else // if there wasn't last data of transfere
|
else // if there wasn't last data of transfere
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
end
|
end
|
3'b001 : // If writting of one data is retried
|
3'b001 : // If writting of one data is retried
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
|
addr_count <= 1'b0 ;
|
addr_count <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
retried_d <= 1'b1 ; // there was a retry
|
retried_d <= 1'b1 ; // there was a retry
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
if(rty_counter_max_value) // If retry counter reached maximum allowed value
|
if(rty_counter_almost_max_value) // If retry counter reached maximum allowed value
|
begin
|
begin
|
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
|
pciw_fifo_renable <= 1'b0 ;
|
|
else // if there wasn't last data of transfere
|
|
pciw_fifo_renable <= 1'b1 ;
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
pci_error_sig_out <= 1'b1 ;
|
pci_error_sig_out <= 1'b1 ;
|
error_source_out <= 1'b1 ; // error ocuerd because of retry counter
|
error_source_out <= 1'b1 ; // error ocuerd because of retry counter
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
pciw_fifo_renable <= 1'b0 ;
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
error_source_out <= 1'b0 ;
|
error_source_out <= 1'b0 ;
|
end
|
end
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
pciw_fifo_renable <= 1'b0 ;
|
|
addr_count <= 1'b0 ;
|
addr_count <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
error_source_out <= 1'b0 ; // if error ocures, error source is from other WB bus side
|
error_source_out <= 1'b0 ; // if error ocures, error source is from other WB bus side
|
if(rty_counter_max_value) // when no WB response and RTY CNT reached maximum allowed value
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
begin
|
begin
|
|
retried_d <= 1'b1 ;
|
|
if (last_data_from_pciw_fifo_reg) // if last data was transfered
|
|
pciw_fifo_renable <= 1'b0 ;
|
|
else // if there wasn't last data of transfere
|
|
pciw_fifo_renable <= 1'b1 ;
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
|
pci_error_sig_out <= 1'b1 ; // signal for error reporting
|
pci_error_sig_out <= 1'b1 ; // signal for error reporting
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
pciw_fifo_renable <= 1'b0 ;
|
|
retried_d <= 1'b0 ;
|
n_state <= S_WRITE ; // stay in S_WRITE state to wait WB to response
|
n_state <= S_WRITE ; // stay in S_WRITE state to wait WB to response
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
pci_error_sig_out <= 1'b0 ;
|
pci_error_sig_out <= 1'b0 ;
|
end
|
end
|
end
|
end
|
| Line 806... |
Line 744... |
wb_we_o <= 1'b1 ;
|
wb_we_o <= 1'b1 ;
|
wb_cyc_o <= 1'b1 ;
|
wb_cyc_o <= 1'b1 ;
|
end
|
end
|
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
|
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
|
begin
|
begin
|
|
`ifdef REGISTER_WBM_OUTPUTS
|
|
pciw_fifo_renable <= !last_data_from_pciw_fifo_reg ; // put out next data (untill last data or FIFO empty)
|
|
`else
|
pciw_fifo_renable <= 1'b1 ; // put out next data (untill last data or FIFO empty)
|
pciw_fifo_renable <= 1'b1 ; // put out next data (untill last data or FIFO empty)
|
|
`endif
|
last_data_transferred <= 1'b1 ; // after exiting this state, negedge of this signal is used
|
last_data_transferred <= 1'b1 ; // after exiting this state, negedge of this signal is used
|
// Default values for signals not used in this state
|
// Default values for signals not used in this state
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control <= 4'h0 ;
|
addr_into_cnt <= 1'b0 ;
|
addr_into_cnt <= 1'b0 ;
|
| Line 891... |
Line 833... |
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control <= 4'h0 ;
|
addr_count <= 1'b0 ;
|
addr_count <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
wait_for_wb_response <= 1'b0 ;
|
case ({first_wb_data_access, rty_counter_max_value})
|
case ({first_wb_data_access, rty_counter_almost_max_value})
|
2'b10 :
|
2'b10 :
|
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
|
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
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| Line 923... |
Line 865... |
default :
|
default :
|
begin
|
begin
|
addr_count <= 1'b0 ;
|
addr_count <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_count_enable <= 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
read_rty_cnt_exp_out <= 1'b0 ;
|
retried_d <= 1'b0 ;
|
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
|
if(rty_counter_max_value) // when no WB response and RTY CNT reached maximum allowed value
|
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
|
begin
|
begin
|
|
retried_d <= 1'b1 ;
|
n_state <= S_TURN_ARROUND ; // go here to stop read request
|
n_state <= S_TURN_ARROUND ; // go here to stop read request
|
pcir_fifo_wenable <= 1'b1 ;
|
pcir_fifo_wenable <= 1'b1 ;
|
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
|
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
|
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
|
| Line 938... |
Line 880... |
last_data_transferred <= 1'b1 ;
|
last_data_transferred <= 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
wb_read_done <= 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
retried_d <= 1'b0 ;
|
n_state <= S_READ ; // stay in S_READ state to wait WB to response
|
n_state <= S_READ ; // stay in S_READ state to wait WB to response
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_wenable <= 1'b0 ;
|
pcir_fifo_control <= 4'h0 ;
|
pcir_fifo_control <= 4'h0 ;
|
last_data_transferred <= 1'b0 ;
|
last_data_transferred <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
wb_read_done <= 1'b0 ;
|
| Line 1074... |
Line 1017... |
|
|
assign ADR_O = addr_cnt_out ;
|
assign ADR_O = addr_cnt_out ;
|
|
|
`ifdef REGISTER_WBM_OUTPUTS
|
`ifdef REGISTER_WBM_OUTPUTS
|
|
|
|
reg no_sel_o_change_due_rty;
|
reg wb_cyc_reg ;
|
reg wb_cyc_reg ;
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
|
no_sel_o_change_due_rty <= 1'b0;
|
CYC_O <= 1'h0 ;
|
CYC_O <= 1'h0 ;
|
STB_O <= 1'h0 ;
|
STB_O <= 1'h0 ;
|
WE_O <= 1'h0 ;
|
WE_O <= 1'h0 ;
|
CAB_O <= 1'h0 ;
|
CAB_O <= 1'h0 ;
|
MDATA_O <= 32'h0 ;
|
MDATA_O <= 32'h0 ;
|
| Line 1093... |
Line 1038... |
pcir_fifo_wenable_out <= 1'b0 ;
|
pcir_fifo_wenable_out <= 1'b0 ;
|
pcir_fifo_control_out <= 1'b0 ;
|
pcir_fifo_control_out <= 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
if (w_attempt)
|
|
if (ACK_I || ERR_I || last_data_transferred)
|
|
no_sel_o_change_due_rty <= 1'b0;
|
|
else if (retry)
|
|
no_sel_o_change_due_rty <= 1'b1;
|
if (wb_cyc_o)
|
if (wb_cyc_o)
|
begin
|
begin // retry = RTY_I || set_retry
|
CYC_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
|
CYC_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
CAB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
|
CAB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
|
STB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
|
STB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
|
end
|
end
|
WE_O <= wb_we_o ;
|
WE_O <= wb_we_o ;
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
MDATA_O <= pciw_fifo_addr_data_in ;
|
|
if (w_attempt)
|
|
begin
|
|
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
|
|
SEL_O <= ~pciw_fifo_cbe_in ;
|
|
end
|
|
else
|
|
begin
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
|
SEL_O <= wb_sel_o ;
|
SEL_O <= wb_sel_o ;
|
|
end
|
wb_cyc_reg <= wb_cyc_o ;
|
wb_cyc_reg <= wb_cyc_o ;
|
wb_read_done_out <= wb_read_done ;
|
wb_read_done_out <= wb_read_done ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_data_out <= MDATA_I ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
pcir_fifo_control_out <= pcir_fifo_control ;
|
