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[/] [pci/] [tags/] [rel_00/] [rtl/] [verilog/] [wbw_fifo_control.v] - Diff between revs 2 and 6
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "constants.v"
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`include "constants.v"
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`include "timescale.v"
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`ifdef FPGA
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`ifdef FPGA
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// fifo design in FPGA will be synchronous
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// fifo design in FPGA will be synchronous
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`ifdef SYNCHRONOUS
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`ifdef SYNCHRONOUS
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`else
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`else
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`define SYNCHRONOUS
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`define SYNCHRONOUS
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