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[/] [pci/] [tags/] [rel_1/] [rtl/] [verilog/] [pci_target32_devs_crit.v] - Diff between revs 6 and 21
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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`include "constants.v"
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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module PCI_TARGET32_DEVS_CRIT
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module PCI_TARGET32_DEVS_CRIT
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(
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(
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devs_w,
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devs_w,
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devs_w_frm,
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devs_w_frm,
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