URL
https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [rel_1/] [rtl/] [verilog/] [wb_master.v] - Diff between revs 2 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 2 |
Rev 6 |
Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
|
// New project directory structure
|
|
//
|
//
|
//
|
|
|
`define FSM_BITS 3 // number of bits needed for FSM states
|
`define FSM_BITS 3 // number of bits needed for FSM states
|
|
|
|
|
`include "bus_commands.v"
|
`include "bus_commands.v"
|
`include "constants.v"
|
`include "constants.v"
|
|
`include "timescale.v"
|
|
|
module WB_MASTER ( wb_clock_in, // CLK_I
|
module WB_MASTER ( wb_clock_in, // CLK_I
|
reset_in, // RST_I
|
reset_in, // RST_I
|
|
|
pci_tar_read_request,
|
pci_tar_read_request,
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.