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Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/01/21 16:06:56 mihad
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// Bug fixes, testcases added.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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| Line 58... |
Line 61... |
// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "pci_constants.v"
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`include "pci_constants.v"
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module PCI_MASTER32_SM
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module pci_master32_sm
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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// arbitration
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// arbitration
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| Line 343... |
Line 346... |
wire force_frame = ~sm_idle ;
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wire force_frame = ~sm_idle ;
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// slow signal for frame calculated from various registers in the core
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// slow signal for frame calculated from various registers in the core
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wire slow_frame = last_in || (latency_time_out && pci_gnt_in) || (next_last_in && sm_data_phases) || mabort1 ;
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wire slow_frame = last_in || (latency_time_out && pci_gnt_in) || (next_last_in && sm_data_phases) || mabort1 ;
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// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted
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// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted
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// (STOP)
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// (STOP)
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FRAME_CRIT frame_iob_feed
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pci_frame_crit frame_iob_feed
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(
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(
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.pci_frame_out (pci_frame_out),
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.pci_frame_out (pci_frame_out),
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.force_frame_in (force_frame),
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.force_frame_in (force_frame),
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.slow_frame_in (slow_frame),
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.slow_frame_in (slow_frame),
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.pci_stop_in (pci_stop_in)
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.pci_stop_in (pci_stop_in)
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| Line 356... |
Line 359... |
// frame IOB flip flop's clock enable signal
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// frame IOB flip flop's clock enable signal
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// slow clock enable - calculated from internal - non critical paths
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// slow clock enable - calculated from internal - non critical paths
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wire frame_load_slow = sm_idle || sm_address || mabort1 ;
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wire frame_load_slow = sm_idle || sm_address || mabort1 ;
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// critical clock enable for frame IOB in separate module - target response signals actually allow frame value change - critical timing
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// critical clock enable for frame IOB in separate module - target response signals actually allow frame value change - critical timing
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FRAME_LOAD_CRIT frame_iob_ce
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pci_frame_load_crit frame_iob_ce
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(
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(
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.pci_frame_load_out (pci_frame_load_out),
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.pci_frame_load_out (pci_frame_load_out),
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.sm_data_phases_in (sm_data_phases),
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.sm_data_phases_in (sm_data_phases),
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.frame_load_slow_in (frame_load_slow),
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.frame_load_slow_in (frame_load_slow),
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.pci_trdy_in (pci_trdy_in),
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.pci_trdy_in (pci_trdy_in),
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| Line 370... |
Line 373... |
// IRDY driving
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// IRDY driving
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// non critical path for IRDY calculation
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// non critical path for IRDY calculation
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wire irdy_slow = pci_frame_out_in && mabort1 || mabort2 ;
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wire irdy_slow = pci_frame_out_in && mabort1 || mabort2 ;
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// critical path in separate module
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// critical path in separate module
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IRDY_OUT_CRIT irdy_iob_feed
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pci_irdy_out_crit irdy_iob_feed
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(
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(
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.pci_irdy_out (pci_irdy_out),
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.pci_irdy_out (pci_irdy_out),
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.irdy_slow_in (irdy_slow),
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.irdy_slow_in (irdy_slow),
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.pci_frame_out_in (pci_frame_out_in),
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.pci_frame_out_in (pci_frame_out_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_trdy_in (pci_trdy_in),
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| Line 413... |
Line 416... |
// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or
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// when address phase is about to be finished
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// when address phase is about to be finished
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wire ad_load_slow = sm_address ;
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wire ad_load_slow = sm_address ;
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wire ad_load_on_grant = sm_idle && pci_frame_in && pci_irdy_in ;
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wire ad_load_on_grant = sm_idle && pci_frame_in && pci_irdy_in ;
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MAS_AD_LOAD_CRIT mas_ad_load_feed
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pci_mas_ad_load_crit mas_ad_load_feed
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(
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(
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.ad_load_out (ad_load_out),
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.ad_load_out (ad_load_out),
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.ad_load_in (ad_load_slow),
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.ad_load_in (ad_load_slow),
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.ad_load_on_grant_in (ad_load_on_grant),
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.ad_load_on_grant_in (ad_load_on_grant),
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.pci_gnt_in (pci_gnt_in)
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.pci_gnt_in (pci_gnt_in)
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| Line 440... |
Line 443... |
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// a bit more critical change state enable is calculated with GNT signal
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// a bit more critical change state enable is calculated with GNT signal
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wire ch_state_med = ch_state_slow || sm_idle && u_have_pci_bus && req_in && rdy_in ;
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wire ch_state_med = ch_state_slow || sm_idle && u_have_pci_bus && req_in && rdy_in ;
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// most critical change state enable - calculated from target response signals
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// most critical change state enable - calculated from target response signals
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MAS_CH_STATE_CRIT state_machine_ce
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pci_mas_ch_state_crit state_machine_ce
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(
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(
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.change_state_out (change_state),
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.change_state_out (change_state),
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.ch_state_med_in (ch_state_med),
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.ch_state_med_in (ch_state_med),
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.sm_data_phases_in (sm_data_phases),
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.sm_data_phases_in (sm_data_phases),
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.pci_trdy_in (pci_trdy_in),
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.pci_trdy_in (pci_trdy_in),
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| Line 460... |
Line 463... |
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wire ad_en_slow = do_write && ( sm_address || ( sm_data_phases && !( ( pci_frame_out_in && mabort1 ) || mabort2 ) ) ) ;
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wire ad_en_slow = do_write && ( sm_address || ( sm_data_phases && !( ( pci_frame_out_in && mabort1 ) || mabort2 ) ) ) ;
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wire ad_en_on_grant = ( sm_idle && pci_frame_in && pci_irdy_in ) || sm_turn_arround ;
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wire ad_en_on_grant = ( sm_idle && pci_frame_in && pci_irdy_in ) || sm_turn_arround ;
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// critical timing ad enable - calculated from grant input
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// critical timing ad enable - calculated from grant input
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MAS_AD_EN_CRIT ad_iob_oe_feed
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pci_mas_ad_en_crit ad_iob_oe_feed
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(
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(
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.pci_ad_en_out (pci_ad_en_out),
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.pci_ad_en_out (pci_ad_en_out),
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.ad_en_slow_in (ad_en_slow),
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.ad_en_slow_in (ad_en_slow),
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.ad_en_on_grant_in (ad_en_on_grant),
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.ad_en_on_grant_in (ad_en_on_grant),
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.pci_gnt_in (pci_gnt_in)
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.pci_gnt_in (pci_gnt_in)
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| Line 474... |
Line 477... |
wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ;
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wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ;
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wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ;
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wire cbe_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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wire cbe_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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// most critical cbe enable in separate module - calculated with most critical target inputs
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// most critical cbe enable in separate module - calculated with most critical target inputs
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CBE_EN_CRIT cbe_iob_feed
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pci_cbe_en_crit cbe_iob_feed
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(
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(
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.pci_cbe_en_out (pci_cbe_en_out),
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.pci_cbe_en_out (pci_cbe_en_out),
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.cbe_en_slow_in (cbe_en_slow),
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.cbe_en_slow_in (cbe_en_slow),
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.cbe_en_keep_in (cbe_en_keep),
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.cbe_en_keep_in (cbe_en_keep),
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.pci_stop_in (pci_stop_in),
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.pci_stop_in (pci_stop_in),
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| Line 492... |
Line 495... |
// frame enable driving - sometimes it's calculated from non critical paths
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// frame enable driving - sometimes it's calculated from non critical paths
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wire frame_en_slow = (sm_idle && u_have_pci_bus && req_in && rdy_in) || sm_address || (sm_data_phases && ~pci_frame_out_in) ;
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wire frame_en_slow = (sm_idle && u_have_pci_bus && req_in && rdy_in) || sm_address || (sm_data_phases && ~pci_frame_out_in) ;
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wire frame_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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wire frame_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ;
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// most critical frame enable - calculated from heavily constrained target inputs in separate module
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// most critical frame enable - calculated from heavily constrained target inputs in separate module
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FRAME_EN_CRIT frame_iob_en_feed
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pci_frame_en_crit frame_iob_en_feed
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(
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(
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.pci_frame_en_out (pci_frame_en_out),
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.pci_frame_en_out (pci_frame_en_out),
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.frame_en_slow_in (frame_en_slow),
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.frame_en_slow_in (frame_en_slow),
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.frame_en_keep_in (frame_en_keep),
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.frame_en_keep_in (frame_en_keep),
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.pci_stop_in (pci_stop_in),
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.pci_stop_in (pci_stop_in),
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