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Line 39... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log
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// $Log: not supported by cvs2svn $
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "pci_constants.v"
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`include "pci_constants.v"
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| Line 56... |
Line 56... |
rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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// flush_in, // not used
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almost_full_out,
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almost_full_out,
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full_out,
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full_out,
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almost_empty_out,
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almost_empty_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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| Line 80... |
Line 79... |
input renable_in, wenable_in;
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input renable_in, wenable_in;
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// reset input
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// reset input
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input reset_in;
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input reset_in;
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// flush input
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//input flush_in ; // not used
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// almost full and empy status outputs
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// almost full and empy status outputs
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output almost_full_out, almost_empty_out;
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output almost_full_out, almost_empty_out;
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// full and empty status outputs
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// full and empty status outputs
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output full_out, empty_out;
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output full_out, empty_out;
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| Line 107... |
Line 103... |
reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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| Line 122... |
Line 119... |
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FFs for registered empty and full flags
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// write allow - writes are allowed when fifo is not full
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wire empty ;
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assign wallow_out = wenable_in & ~full_out ;
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wire full ;
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// registered almost_empty and almost_full flags
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wire almost_empty ;
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wire almost_full ;
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && !full ;
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// write allow output assignment
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assign wallow_out = wallow ;
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// read allow wire
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wire rallow ;
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// full output assignment
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assign full_out = full ;
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// almost full output assignment
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assign almost_full_out = almost_full && !full ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in /*|| flush_in*/ ; // flush not used for write fifo
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wire clear = reset_in ;
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assign empty_out = empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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assign rallow_out = rallow ;
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// almost empty output assignment
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assign almost_empty_out = almost_empty && !empty ;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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// read address mux - when read is performed, next address is driven, so next data is available immediately after read
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// read address mux - when read is performed, next address is driven, so next data is available immediately after read
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// this is convenient for zero wait stait bursts
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// this is convenient for zero wait stait bursts
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
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// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr_plus_one <= #`FF_DELAY 5 ;
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raddr <= #`FF_DELAY 4 ;
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raddr <= #`FF_DELAY 4 ;
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end
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end
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else if (rallow)
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else if (rallow_out)
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begin
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begin
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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end
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end
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| Line 196... |
Line 165... |
// grey coded address pipeline for status generation in read clock domain
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// grey coded address pipeline for status generation in read clock domain
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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rgrey_minus2 <= #`FF_DELAY 0 ;
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rgrey_minus2 <= #1 0 ;
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rgrey_minus1 <= #`FF_DELAY 1 ;
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rgrey_minus1 <= #`FF_DELAY 1 ;
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rgrey_addr <= #`FF_DELAY 3 ;
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rgrey_addr <= #1 3 ;
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rgrey_next <= #`FF_DELAY 2 ;
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rgrey_next <= #`FF_DELAY 2 ;
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end
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end
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else
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else
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if (rallow)
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if (rallow_out)
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begin
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begin
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rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
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rgrey_minus2 <= #1 rgrey_minus1 ;
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #1 rgrey_next ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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Write address control consists of write address counter and 2 Grey Code Registers:
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Write address control consists of write address counter and 3 Grey Code Registers:
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- wgrey_minus1 represents previous Grey coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_next represents Grey Coded next write address
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- wgrey_next represents Grey Coded next write address
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----------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------*/
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// grey coded address pipeline for status generation in write clock domain
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// grey coded address pipeline for status generation in write clock domain
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wgrey_addr <= #`FF_DELAY 3 ;
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wgrey_minus1 <= #`FF_DELAY 1 ;
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wgrey_addr <= #1 3 ;
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wgrey_next <= #`FF_DELAY 2 ;
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wgrey_next <= #`FF_DELAY 2 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow_out)
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begin
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begin
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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wgrey_addr <= #1 wgrey_next ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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end
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end
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// write address counter - nothing special except initial value
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// write address counter - nothing special except initial value
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| Line 239... |
Line 211... |
begin
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begin
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if (clear)
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if (clear)
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// initial value 5
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// initial value 5
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waddr <= #`FF_DELAY 4 ;
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waddr <= #`FF_DELAY 4 ;
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else
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else
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if (wallow)
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if (wallow_out)
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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end
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end
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Full control:
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Gray coded address of read address decremented by two is synchronized to write clock domain and compared to:
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Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.
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- previous grey coded write address - if they are equal, the fifo is full
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If they are equal, fifo is full.
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- gray coded write address. If they are equal, fifo is almost full.
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Almost full control:
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Gray coded address of read address decremented by two is synchronized to write clock domain and compared to Gray coded write
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- grey coded next write address. If they are equal, the fifo has two free locations left.
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address. If they are equal, fifo is almost full.
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Two left control:
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If Gray coded next write address is equal to Gray coded address of read address decremented by two, the fifo has two free
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locations left.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
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wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
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reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
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synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_rgrey_addr
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(
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.data_in (rgrey_addr),
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.clk_out (wclock_in),
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.sync_data_out (wclk_sync_rgrey_addr),
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.async_reset (clear)
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) ;
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
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synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
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(
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(
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.data_in (rgrey_minus2),
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.data_in (rgrey_minus2),
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.clk_out (wclock_in),
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.clk_out (wclock_in),
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.sync_data_out (wclk_sync_rgrey_minus2),
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.sync_data_out (wclk_sync_rgrey_minus2),
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| Line 281... |
Line 238... |
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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wclk_rgrey_addr <= #`FF_DELAY 3 ;
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wclk_rgrey_minus2 <= #`FF_DELAY 0 ;
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wclk_rgrey_minus2 <= #`FF_DELAY 0 ;
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end
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end
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else
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else
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begin
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begin
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wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ;
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wclk_rgrey_minus2 <= #`FF_DELAY wclk_sync_rgrey_minus2 ;
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wclk_rgrey_minus2 <= #`FF_DELAY wclk_sync_rgrey_minus2 ;
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end
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end
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end
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end
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assign full = (wgrey_next == wclk_rgrey_addr) ;
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assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ;
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assign almost_full = (wgrey_addr == wclk_rgrey_minus2) ;
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assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ;
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assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
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assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
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/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Empty control:
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Empty control:
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
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| Line 322... |
Line 277... |
rclk_wgrey_addr <= #`FF_DELAY 3 ;
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rclk_wgrey_addr <= #`FF_DELAY 3 ;
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else
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else
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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end
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end
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assign almost_empty = (rgrey_next == rclk_wgrey_addr) ;
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assign almost_empty_out = (rgrey_next == rclk_wgrey_addr) ;
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assign empty = (rgrey_addr == rclk_wgrey_addr) ;
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assign empty_out = (rgrey_addr == rclk_wgrey_addr) ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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