Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2003/01/27 16:49:31 mihad
|
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
|
//
|
// Revision 1.8 2003/01/21 16:06:56 mihad
|
// Revision 1.8 2003/01/21 16:06:56 mihad
|
// Bug fixes, testcases added.
|
// Bug fixes, testcases added.
|
//
|
//
|
// Revision 1.7 2002/09/24 19:09:17 mihad
|
// Revision 1.7 2002/09/24 19:09:17 mihad
|
// Number of state bits define was removed
|
// Number of state bits define was removed
|
Line 98... |
Line 101... |
// address, data, bus command, byte enable in/outs
|
// address, data, bus command, byte enable in/outs
|
pci_ad_reg_in,
|
pci_ad_reg_in,
|
pci_ad_out,
|
pci_ad_out,
|
pci_ad_en_out,
|
pci_ad_en_out,
|
pci_cbe_reg_in,
|
pci_cbe_reg_in,
|
|
pci_cbe_in,
|
bckp_trdy_en_in,
|
bckp_trdy_en_in,
|
bckp_devsel_in,
|
bckp_devsel_in,
|
bckp_trdy_in,
|
bckp_trdy_in,
|
bckp_stop_in,
|
bckp_stop_in,
|
pci_trdy_reg_in,
|
pci_trdy_reg_in,
|
Line 113... |
Line 117... |
bc_out,
|
bc_out,
|
bc0_out,
|
bc0_out,
|
data_out,
|
data_out,
|
data_in,
|
data_in,
|
be_out,
|
be_out,
|
|
next_be_out,
|
req_out,
|
req_out,
|
rdy_out,
|
rdy_out,
|
addr_phase_out,
|
addr_phase_out,
|
bckp_devsel_out,
|
bckp_devsel_out,
|
bckp_trdy_out,
|
bckp_trdy_out,
|
Line 186... |
Line 191... |
// address, data, bus command, byte enable in/outs
|
// address, data, bus command, byte enable in/outs
|
input [31:0] pci_ad_reg_in ;
|
input [31:0] pci_ad_reg_in ;
|
output [31:0] pci_ad_out ;
|
output [31:0] pci_ad_out ;
|
output pci_ad_en_out ;
|
output pci_ad_en_out ;
|
input [3:0] pci_cbe_reg_in ;
|
input [3:0] pci_cbe_reg_in ;
|
|
input [3:0] pci_cbe_in ;
|
input bckp_trdy_en_in ;
|
input bckp_trdy_en_in ;
|
input bckp_devsel_in ;
|
input bckp_devsel_in ;
|
input bckp_trdy_in ;
|
input bckp_trdy_in ;
|
input bckp_stop_in ;
|
input bckp_stop_in ;
|
input pci_trdy_reg_in ;
|
input pci_trdy_reg_in ;
|
Line 205... |
Line 211... |
output [3:0] bc_out ; // current request bus command output - registered
|
output [3:0] bc_out ; // current request bus command output - registered
|
output bc0_out ; // current cycle RW signal output
|
output bc0_out ; // current cycle RW signal output
|
input [31:0] data_in ; // for read operations - current dataphase data input
|
input [31:0] data_in ; // for read operations - current dataphase data input
|
output [31:0] data_out ; // for write operations - current request data output - registered
|
output [31:0] data_out ; // for write operations - current request data output - registered
|
output [3:0] be_out ; // current dataphase byte enable outputs - registered
|
output [3:0] be_out ; // current dataphase byte enable outputs - registered
|
|
output [3:0] next_be_out ; // next dataphase byte enable outputs - NOT registered
|
// Port connection control signals from PCI FSM
|
// Port connection control signals from PCI FSM
|
output req_out ; // Read is requested to WB master
|
output req_out ; // Read is requested to WB master
|
output rdy_out ; // DATA / ADDRESS selection when read or write - registered
|
output rdy_out ; // DATA / ADDRESS selection when read or write - registered
|
output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
|
output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
|
output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
|
output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
|
Line 524... |
Line 531... |
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire trdy_w_frm = (
|
wire trdy_w_frm = (
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (!rw_cbe0 && !pcir_fifo_data_err_in))
|
(state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in &&
|
|
((~rw_cbe0 && ~pcir_fifo_data_err_in) || rw_cbe0))
|
) ;
|
) ;
|
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
|
wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
Line 736... |
Line 744... |
// data and address outputs assignments!
|
// data and address outputs assignments!
|
assign pci_ad_out = data_in ;
|
assign pci_ad_out = data_in ;
|
|
|
assign data_out = pci_ad_reg_in ;
|
assign data_out = pci_ad_reg_in ;
|
assign be_out = pci_cbe_reg_in ;
|
assign be_out = pci_cbe_reg_in ;
|
|
assign next_be_out = pci_cbe_in ;
|
assign address_out = pci_ad_reg_in ;
|
assign address_out = pci_ad_reg_in ;
|
assign bc_out = pci_cbe_reg_in ;
|
assign bc_out = pci_cbe_reg_in ;
|
assign bc0_out = rw_cbe0 ;
|
assign bc0_out = rw_cbe0 ;
|
|
|
|
|