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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/01/21 16:06:56 mihad
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// Bug fixes, testcases added.
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//
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// Revision 1.4 2002/09/30 17:22:45 mihad
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// Revision 1.4 2002/09/30 17:22:45 mihad
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
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//
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//
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// Revision 1.3 2002/08/13 11:03:53 mihad
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// Revision 1.3 2002/08/13 11:03:53 mihad
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
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// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
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// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
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// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
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// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// WB_FIFO_RAM_ADDR_LENGTH.
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// WB_FIFO_RAM_ADDR_LENGTH.
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`define WBW_ADDR_LENGTH 6
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`define WBW_ADDR_LENGTH 3
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`define WBR_ADDR_LENGTH 4
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`define WBR_ADDR_LENGTH 5
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`define PCIW_ADDR_LENGTH 3
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`define PCIW_ADDR_LENGTH 3
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`define PCIR_ADDR_LENGTH 3
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`define PCIR_ADDR_LENGTH 3
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//`define FPGA
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`define FPGA
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//`define XILINX
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`define XILINX
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//`define WB_RAM_DONT_SHARE
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//`define WB_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef FPGA
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`ifdef XILINX
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define PCI_XILINX_RAMB4
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//`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`endif
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`else
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define ACTIVE_LOW_OE
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`define ACTIVE_LOW_OE
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//`define ACTIVE_HIGH_OE
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//`define ACTIVE_HIGH_OE
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// HOST/GUEST implementation selection - see design document and specification for description of each implementation
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// HOST/GUEST implementation selection - see design document and specification for description of each implementation
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// only one can be defined at same time
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// only one can be defined at same time
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//`define GUEST
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`define GUEST
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`define GUEST
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//`define HOST
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// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
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// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
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// - ENABLED Read-Only access from WISHBONE for GUEST bridges
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// - ENABLED Read-Only access from WISHBONE for GUEST bridges
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// - ENABLED Read-Only access from PCI for HOST bridges
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// - ENABLED Read-Only access from PCI for HOST bridges
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// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
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// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
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// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
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// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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// smaller the number here, faster the decoder operation
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`define PCI_NUM_OF_DEC_ADDR_LINES 20
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`define PCI_NUM_OF_DEC_ADDR_LINES 12
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// no. of PCI Target IMAGES
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// no. of PCI Target IMAGES
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// - PCI provides 6 base address registers for image implementation.
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// - PCI provides 6 base address registers for image implementation.
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// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
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// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
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// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
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// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`define PCI_IMAGE0
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`define PCI_IMAGE0
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`endif
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`endif
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`endif
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`endif
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`define PCI_IMAGE2
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//`define PCI_IMAGE2
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`define PCI_IMAGE3
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//`define PCI_IMAGE3
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`define PCI_IMAGE4
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//`define PCI_IMAGE4
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`define PCI_IMAGE5
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//`define PCI_IMAGE5
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// initial value for PCI image address masks. Address masks can be defined in enabled state,
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// initial value for PCI image address masks. Address masks can be defined in enabled state,
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// to allow device independent software to detect size of image and map base addresses to
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// to allow device independent software to detect size of image and map base addresses to
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// memory space. If initial mask for an image is defined as 0, then device independent software
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// memory space. If initial mask for an image is defined as 0, then device independent software
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// won't detect base address implemented and device dependent software will have to configure
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// won't detect base address implemented and device dependent software will have to configure
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// address masks as well as base addresses!
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// address masks as well as base addresses!
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`define PCI_AM0 20'hffff_e
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`define PCI_AM0 20'hffff_f
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`define PCI_AM1 20'hffff_c
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`define PCI_AM1 20'hffff_f
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`define PCI_AM2 20'hffff_8
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`define PCI_AM2 20'hffff_8
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`define PCI_AM3 20'hffff_0
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`define PCI_AM3 20'hffff_0
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`define PCI_AM4 20'hfffe_0
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`define PCI_AM4 20'hfffe_0
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`define PCI_AM5 20'h0000_0
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`define PCI_AM5 20'h0000_0
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// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
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// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
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// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
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// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
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// Device independent software sets the base addresses acording to MEMORY or IO maping!
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// Device independent software sets the base addresses acording to MEMORY or IO maping!
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`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
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`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
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`define PCI_BA1_MEM_IO 1'b1
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`define PCI_BA1_MEM_IO 1'b0
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`define PCI_BA2_MEM_IO 1'b0
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`define PCI_BA2_MEM_IO 1'b0
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`define PCI_BA3_MEM_IO 1'b1
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`define PCI_BA3_MEM_IO 1'b1
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`define PCI_BA4_MEM_IO 1'b0
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`define PCI_BA4_MEM_IO 1'b0
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`define PCI_BA5_MEM_IO 1'b1
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`define PCI_BA5_MEM_IO 1'b1
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// number defined here specifies how many MS bits in WB address are compared with base address, to decode
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// number defined here specifies how many MS bits in WB address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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// smaller the number here, faster the decoder operation
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`define WB_NUM_OF_DEC_ADDR_LINES 20
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`define WB_NUM_OF_DEC_ADDR_LINES 3
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// no. of WISHBONE Slave IMAGES
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// no. of WISHBONE Slave IMAGES
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// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
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// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
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// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
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// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
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// WB Image 1 is always implemented and user doesnt need to specify its definition
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// WB Image 1 is always implemented and user doesnt need to specify its definition
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// WB images' 2 through 5 implementation by defining each one.
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// WB images' 2 through 5 implementation by defining each one.
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//`define WB_IMAGE2
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//`define WB_IMAGE2
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`define WB_IMAGE3
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//`define WB_IMAGE3
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`define WB_IMAGE4
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//`define WB_IMAGE4
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//`define WB_IMAGE5
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//`define WB_IMAGE5
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// If this define is commented out, then address translation will not be implemented.
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// If this define is commented out, then address translation will not be implemented.
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// addresses will pass through bridge unchanged, regardles of address translation enable bits.
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// addresses will pass through bridge unchanged, regardles of address translation enable bits.
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// Address translation also slows down the decoding
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// Address translation also slows down the decoding
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//`define ADDR_TRAN_IMPL
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//`define ADDR_TRAN_IMPL
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
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// slower decode speed can be used, to provide enough time for address to be decoded.
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// slower decode speed can be used, to provide enough time for address to be decoded.
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//`define WB_DECODE_FAST
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`define WB_DECODE_FAST
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`define WB_DECODE_MEDIUM
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//`define WB_DECODE_MEDIUM
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//`define WB_DECODE_SLOW
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//`define WB_DECODE_SLOW
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
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`define WB_CONFIGURATION_BASE 20'hF300_0
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`define WB_CONFIGURATION_BASE 20'hF300_0
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